JPS6430247A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6430247A
JPS6430247A JP18639887A JP18639887A JPS6430247A JP S6430247 A JPS6430247 A JP S6430247A JP 18639887 A JP18639887 A JP 18639887A JP 18639887 A JP18639887 A JP 18639887A JP S6430247 A JPS6430247 A JP S6430247A
Authority
JP
Japan
Prior art keywords
element substrate
substrate
oxide film
film
impurity diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18639887A
Other languages
Japanese (ja)
Inventor
Hiroshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18639887A priority Critical patent/JPS6430247A/en
Publication of JPS6430247A publication Critical patent/JPS6430247A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent an element substrate from electrical floatation and thereby to suppress fluctuations in the element substrate potential at the switching-on of the elements by a method wherein a layer serving virtually as a conductive layer is provided on the element substrate on its side nearer to an insulating substrate. CONSTITUTION:Into the side of an element substrate 1 in contact with an insulating substrate 4, As<+> is driven, producing an n<-> impurity diffusion layer 2 (to virtually serve as a conductive layer) near the surface. The element substrate 1 and a supporting substrate 3, made for example of n<+> silicon, are bonded together, and the combination is subjected to annealing. The surface (the side nearer to the element substrate 1) is converted into a mirror-finished surface 1a, a through-oxide film 5 is formed on its surface, and implantation of P<+> ions is accomplished for the formation of a substrate contact section 6 reaching the impurity diffusion layer 2. The through-oxide film 5 is removed and, by using the conventional technique, a field oxide film 7, a source electrode 8, a drain electrode 9, a gate electrode 10, an interlayer insulating film 11, aluminum layers 121-123, and a covering film 13 are provided.
JP18639887A 1987-07-24 1987-07-24 Semiconductor device Pending JPS6430247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18639887A JPS6430247A (en) 1987-07-24 1987-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18639887A JPS6430247A (en) 1987-07-24 1987-07-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6430247A true JPS6430247A (en) 1989-02-01

Family

ID=16187702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18639887A Pending JPS6430247A (en) 1987-07-24 1987-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6430247A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238875A (en) * 1990-09-06 1993-08-24 Shin-Etsu Handotai Co., Ltd. Method of producing a bonded wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238875A (en) * 1990-09-06 1993-08-24 Shin-Etsu Handotai Co., Ltd. Method of producing a bonded wafer

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