DE69032215T2 - Trockenätzen von Vias in beschichteten integrierten Schaltungen - Google Patents

Trockenätzen von Vias in beschichteten integrierten Schaltungen

Info

Publication number
DE69032215T2
DE69032215T2 DE69032215T DE69032215T DE69032215T2 DE 69032215 T2 DE69032215 T2 DE 69032215T2 DE 69032215 T DE69032215 T DE 69032215T DE 69032215 T DE69032215 T DE 69032215T DE 69032215 T2 DE69032215 T2 DE 69032215T2
Authority
DE
Germany
Prior art keywords
vias
integrated circuits
dry etching
coated integrated
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032215T
Other languages
English (en)
Other versions
DE69032215D1 (de
Inventor
Jerome L Elkind
Patricia B Smith
Larry D Hutchins
Joseph D Luttmer
Rudy L York
Julie S England
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69032215D1 publication Critical patent/DE69032215D1/de
Application granted granted Critical
Publication of DE69032215T2 publication Critical patent/DE69032215T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
DE69032215T 1989-07-10 1990-07-09 Trockenätzen von Vias in beschichteten integrierten Schaltungen Expired - Fee Related DE69032215T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/377,514 US5017511A (en) 1989-07-10 1989-07-10 Method for dry etching vias in integrated circuit layers

Publications (2)

Publication Number Publication Date
DE69032215D1 DE69032215D1 (de) 1998-05-14
DE69032215T2 true DE69032215T2 (de) 1998-08-27

Family

ID=23489408

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032215T Expired - Fee Related DE69032215T2 (de) 1989-07-10 1990-07-09 Trockenätzen von Vias in beschichteten integrierten Schaltungen

Country Status (3)

Country Link
US (1) US5017511A (de)
EP (1) EP0408276B1 (de)
DE (1) DE69032215T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157000A (en) * 1989-07-10 1992-10-20 Texas Instruments Incorporated Method for dry etching openings in integrated circuit layers
EP0503473A3 (en) * 1991-03-12 1992-10-28 Texas Instruments Incorporated Method of dry etching ina1as and ingaas lattice matched to inp
US5300452A (en) * 1991-12-18 1994-04-05 U.S. Philips Corporation Method of manufacturing an optoelectronic semiconductor device
US5318666A (en) * 1993-04-19 1994-06-07 Texas Instruments Incorporated Method for via formation and type conversion in group II and group VI materials
US5416030A (en) * 1993-05-11 1995-05-16 Texas Instruments Incorporated Method of reducing leakage current in an integrated circuit
WO1997029517A2 (de) * 1996-02-05 1997-08-14 Laboratorium Für Physikalische Elektronik Uv-strahlungsdetektor
US6281035B1 (en) * 1997-09-25 2001-08-28 Midwest Research Institute Ion-beam treatment to prepare surfaces of p-CdTe films
US6693038B1 (en) * 1999-02-05 2004-02-17 Taiwan Semiconductor Manufacturing Company Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching
US20110033962A1 (en) * 2006-04-21 2011-02-10 Wavenics Inc. High efficiency led with multi-layer reflector structure and method for fabricating the same
US20090098309A1 (en) * 2007-10-15 2009-04-16 Advantech Global, Ltd In-Situ Etching Of Shadow Masks Of A Continuous In-Line Shadow Mask Vapor Deposition System
CN106784133A (zh) * 2016-11-25 2017-05-31 中国科学院上海技术物理研究所 一种控制碲镉汞刻蚀诱导电学反型层厚度的方法
CN113432778B (zh) * 2021-05-25 2023-09-29 歌尔微电子股份有限公司 Mems差压传感器及其制造方法
CN116741874B (zh) * 2023-05-30 2024-01-09 北京智创芯源科技有限公司 一种在碲镉汞红外探测器芯片上制备接触孔的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821324A (ja) * 1981-07-30 1983-02-08 Agency Of Ind Science & Technol 水素添加した半導体薄膜成長用金属表面基板の前処理方法
US4579609A (en) * 1984-06-08 1986-04-01 Massachusetts Institute Of Technology Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US4734152A (en) * 1986-12-22 1988-03-29 Massachusetts Institute Of Technology Dry etching patterning of electrical and optical materials
FR2615655B1 (fr) * 1987-05-21 1989-06-30 Loic Henry Procede de gravure anisotrope d'un materiau iii-v : application au traitement de surface en vue d'une croissance epitaxiale
US4818326A (en) * 1987-07-16 1989-04-04 Texas Instruments Incorporated Processing apparatus
US4838984A (en) * 1987-07-16 1989-06-13 Texas Instruments Incorporated Method for etching films of mercury-cadmium-telluride and zinc sulfid
JPH01184830A (ja) * 1988-01-13 1989-07-24 Matsushita Electric Ind Co Ltd ドライエッチング方法

Also Published As

Publication number Publication date
EP0408276B1 (de) 1998-04-08
US5017511A (en) 1991-05-21
EP0408276A2 (de) 1991-01-16
DE69032215D1 (de) 1998-05-14
EP0408276A3 (en) 1991-04-03

Similar Documents

Publication Publication Date Title
DE69533998D1 (de) Entwurf von integrierten Halbleiterschaltungen
DE69026164D1 (de) Halbleitende integrierte Schaltung
KR900012345A (ko) 집적 회로 칩
DE69233067D1 (de) Integrierte Schaltungen
DE3855797D1 (de) Integrierte Halbleiterschaltung
KR860000712A (ko) 반도체 집적회로 및 그 회로 패턴 설계방법
DE69032215D1 (de) Trockenätzen von Vias in beschichteten integrierten Schaltungen
DE69028646D1 (de) Störungsvermindernde Schaltungen
DE69326269T2 (de) Herstellungsverfahren von Kontaktöffnungen in integrierten Schaltungen
KR900012359A (ko) 집적회로 칩
BR9002876A (pt) Metodo de circuitos de retencao e travamento de micro-processadores
KR900012519A (ko) 양면배선기판의 제조방법
DE3675236D1 (de) Kontaktloses testen von integrierten schaltungen.
KR890015418A (ko) 반도체 집적회로와 그 제조방법
DE3768881D1 (de) Integrierte schaltungen mit stufenfoermigen dielektrikum.
DE68919290D1 (de) Nasssätzung von ausgehärteten Polyimiden.
DE69031671D1 (de) Integrierte Halbleiterschaltung
DE69731053D1 (de) Prüfung von Schaltungen mit Schmitt-Eingängen
DE68929104D1 (de) Integrierte Halbleiterschaltung
DE3667547D1 (de) Kontaktloses pruefen integrierter schaltungen.
KR900012360A (ko) 반도체 집적회로와 그 제조방법
DE69026226D1 (de) Integrierte Halbleiterschaltung
KR900012518A (ko) 양면배선기판의 제조방법
KR900007103A (ko) 반도체 집적회로와 그 제조방법
DE59010116D1 (de) Verfahren zum Herstellen von integrierten Schaltungen sowie integrierte Schaltung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee