DE69031701D1 - Kodier- und Dekodierschaltung für lauflängenbegrenzte Kodierung - Google Patents

Kodier- und Dekodierschaltung für lauflängenbegrenzte Kodierung

Info

Publication number
DE69031701D1
DE69031701D1 DE69031701T DE69031701T DE69031701D1 DE 69031701 D1 DE69031701 D1 DE 69031701D1 DE 69031701 T DE69031701 T DE 69031701T DE 69031701 T DE69031701 T DE 69031701T DE 69031701 D1 DE69031701 D1 DE 69031701D1
Authority
DE
Germany
Prior art keywords
coding
decoding circuit
run length
limited
limited coding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031701T
Other languages
English (en)
Other versions
DE69031701T2 (de
Inventor
Hiroyuki Tanaka
Hiroshi Uno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP23318489A external-priority patent/JPH088496B2/ja
Priority claimed from JP23318589A external-priority patent/JP2599998B2/ja
Priority claimed from JP23808789A external-priority patent/JP2599999B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69031701D1 publication Critical patent/DE69031701D1/de
Publication of DE69031701T2 publication Critical patent/DE69031701T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G06T9/005—Statistical coding, e.g. Huffman, run length coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DE69031701T 1989-09-08 1990-09-07 Kodier- und Dekodierschaltung für lauflängenbegrenzte Kodierung Expired - Fee Related DE69031701T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP23318489A JPH088496B2 (ja) 1989-09-08 1989-09-08 変調装置
JP23318589A JP2599998B2 (ja) 1989-09-08 1989-09-08 復調装置
JP23808789A JP2599999B2 (ja) 1989-09-13 1989-09-13 変復調装置

Publications (2)

Publication Number Publication Date
DE69031701D1 true DE69031701D1 (de) 1997-12-18
DE69031701T2 DE69031701T2 (de) 1998-03-12

Family

ID=27331963

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031701T Expired - Fee Related DE69031701T2 (de) 1989-09-08 1990-09-07 Kodier- und Dekodierschaltung für lauflängenbegrenzte Kodierung

Country Status (3)

Country Link
US (1) US5270714A (de)
EP (1) EP0416930B1 (de)
DE (1) DE69031701T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502419A (en) * 1992-06-05 1996-03-26 Canon Kabushiki Kaisha Pulse width modulation signal generation and triangular wave signal generator for the same
KR0141126B1 (ko) * 1992-08-31 1998-07-15 윤종용 디지탈 기록재생시스템에 있어서 코드변환제어장치 및 방법
JP3227901B2 (ja) * 1993-05-21 2001-11-12 ソニー株式会社 変調方法及び復調装置
US5535187A (en) * 1993-12-15 1996-07-09 Intenational Business Machines Corporation High capacity run-length-limited coding system employing asymmetric and even-spaced codes
US5614905A (en) * 1994-01-25 1997-03-25 Crane; Ronald C. High speed serial digital data to analog signal converter
JP3461899B2 (ja) * 1994-03-24 2003-10-27 株式会社ルネサスＬｓｉデザイン 画像変換装置
JP2944440B2 (ja) * 1994-12-27 1999-09-06 日本電気株式会社 時分割多重伝送装置
KR0170681B1 (ko) * 1995-08-09 1999-03-20 김광호 Rll코드 데이터를 위한 부호화 및 복호화장치
WO1997007501A1 (en) * 1995-08-18 1997-02-27 Quantum Corporation Control loops for low power, high speed prml sampling data detection channel
US5960041A (en) * 1995-09-21 1999-09-28 Lucent Technologies Inc. Method and apparatus for generating high rate codes for recording information on a magnetic medium
JP3184083B2 (ja) * 1995-12-15 2001-07-09 日本電気株式会社 チャネル多重分離方法およびチャネル多重分離装置
JP3643425B2 (ja) * 1996-02-29 2005-04-27 富士通株式会社 データ処理方法、データ処理装置及びインターフェイスコントローラ
JPH10322298A (ja) 1997-05-20 1998-12-04 Nec Corp 時分割多重伝送におけるチャネル認識方法及びこれを用いた時分割多重伝送システム
JP3549756B2 (ja) * 1998-12-21 2004-08-04 日本電気株式会社 ブロックインターリーブ回路
US6252419B1 (en) 1999-01-08 2001-06-26 Altera Corporation LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
US7082091B2 (en) * 2001-07-31 2006-07-25 Ricoh Company, Ltd. Information reproducing method judging a multivalued level of a present cell by referring to judged multivalued levels of a preceding cell and an ensuing cell
TW527824B (en) * 2002-03-12 2003-04-11 Via Tech Inc Adative-deflicker processing method and adaptive deflicker filter
TW563353B (en) * 2002-03-12 2003-11-21 Via Tech Inc Clock signal synthesizer with multiple frequency outputs and method for synthesizing clock signal
TW561783B (en) * 2002-03-12 2003-11-11 Via Tech Inc Image processing method and device
US6832173B1 (en) 2002-07-30 2004-12-14 Altera Corporation Testing circuit and method for phase-locked loop
US6867616B1 (en) 2003-06-04 2005-03-15 Altera Corporation Programmable logic device serial interface having dual-use phase-locked loop circuitry
US7019570B2 (en) 2003-09-05 2006-03-28 Altera Corporation Dual-gain loop circuitry for programmable logic device
US7103110B2 (en) * 2003-10-10 2006-09-05 Atmel Corporation Dual phase pulse modulation encoder circuit
US6924678B2 (en) 2003-10-21 2005-08-02 Altera Corporation Programmable phase-locked loop circuitry for programmable logic device
US7091760B1 (en) 2004-02-25 2006-08-15 Altera Corporation DLL with adjustable phase shift using processed control signal
US7075365B1 (en) 2004-04-22 2006-07-11 Altera Corporation Configurable clock network for programmable logic device
US7230495B2 (en) 2004-04-28 2007-06-12 Micron Technology, Inc. Phase-locked loop circuits with reduced lock time
US7436228B1 (en) 2005-12-22 2008-10-14 Altera Corporation Variable-bandwidth loop filter methods and apparatus
US7728674B1 (en) 2006-05-19 2010-06-01 Altera Corporation Voltage-controlled oscillator methods and apparatus
US7683810B2 (en) * 2008-04-23 2010-03-23 Seagate Technology Llc Code design with decreased transition density and reduced running digital sum
US7741980B2 (en) * 2008-09-03 2010-06-22 Seagate Technology Llc Providing running digital sum control in a precoded bit stream using precoder aware encoding
US8514108B2 (en) * 2011-05-25 2013-08-20 Broadcom Corporation Single stage and scalable serializer
CN103365814B (zh) * 2013-06-27 2016-08-17 深圳市汇顶科技股份有限公司 一种串行数据传输方法及其系统

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE30182E (en) * 1969-06-24 1979-12-25 Bell Telephone Laboratories, Incorporated Precoded ternary data transmission
US4496934A (en) * 1980-09-05 1985-01-29 Mitsubishi Denki Kabushiki Kaisha Encoding and decoding systems for binary data
US4413251A (en) * 1981-07-16 1983-11-01 International Business Machines Corporation Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3
US4488142A (en) * 1981-12-31 1984-12-11 International Business Machines Corporation Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3
JPS58146129A (ja) * 1982-02-24 1983-08-31 Usac Electronics Ind Co Ltd 並列・直列変換回路
US4551773A (en) * 1982-07-16 1985-11-05 Sperry Corporation Encoding and decoding apparatus and method utilizing hierarchical code substitution
JPH0714145B2 (ja) * 1983-04-26 1995-02-15 ソニー株式会社 情報変換方法
JPS60113366A (ja) * 1983-11-24 1985-06-19 Sony Corp 情報変換方式
JPH0650590B2 (ja) * 1985-04-27 1994-06-29 富士通株式会社 復合化回路
JPS637051A (ja) * 1986-06-27 1988-01-12 Matsushita Electric Ind Co Ltd 分散型ネツトワ−クの固有情報設定方法
JPS6349789A (ja) * 1986-08-20 1988-03-02 沖電気工業株式会社 表示装置
JPS63144464A (ja) * 1986-12-08 1988-06-16 Fujitsu Ltd デ−タの変復調装置
JPH061608B2 (ja) * 1986-12-08 1994-01-05 富士通株式会社 デ−タの変復調装置
US4864303A (en) * 1987-02-13 1989-09-05 Board Of Trustees Of The University Of Illinois Encoder/decoder system and methodology utilizing conservative coding with block delimiters, for serial communication
JPH01133095A (ja) * 1987-11-17 1989-05-25 Ricoh Co Ltd 表示制御方式

Also Published As

Publication number Publication date
EP0416930B1 (de) 1997-11-12
EP0416930A2 (de) 1991-03-13
EP0416930A3 (en) 1991-11-27
DE69031701T2 (de) 1998-03-12
US5270714A (en) 1993-12-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee