DE69031676T2 - Architektur des Abtastpfads eines Systems - Google Patents

Architektur des Abtastpfads eines Systems

Info

Publication number
DE69031676T2
DE69031676T2 DE69031676T DE69031676T DE69031676T2 DE 69031676 T2 DE69031676 T2 DE 69031676T2 DE 69031676 T DE69031676 T DE 69031676T DE 69031676 T DE69031676 T DE 69031676T DE 69031676 T2 DE69031676 T2 DE 69031676T2
Authority
DE
Germany
Prior art keywords
scan path
primary
architecture
bus
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031676T
Other languages
English (en)
Other versions
DE69031676D1 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/391,751 external-priority patent/US5056093A/en
Priority claimed from US07/391,801 external-priority patent/US5054024A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69031676D1 publication Critical patent/DE69031676D1/de
Application granted granted Critical
Publication of DE69031676T2 publication Critical patent/DE69031676T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Information Transfer Systems (AREA)
DE69031676T 1989-08-09 1990-08-08 Architektur des Abtastpfads eines Systems Expired - Fee Related DE69031676T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/391,751 US5056093A (en) 1989-08-09 1989-08-09 System scan path architecture
US07/391,801 US5054024A (en) 1989-08-09 1989-08-09 System scan path architecture with remote bus controller

Publications (2)

Publication Number Publication Date
DE69031676D1 DE69031676D1 (de) 1997-12-11
DE69031676T2 true DE69031676T2 (de) 1998-03-12

Family

ID=27013620

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031676T Expired - Fee Related DE69031676T2 (de) 1989-08-09 1990-08-08 Architektur des Abtastpfads eines Systems

Country Status (4)

Country Link
EP (1) EP0417905B1 (de)
JP (1) JPH03240851A (de)
KR (1) KR100212256B1 (de)
DE (1) DE69031676T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19917686A1 (de) * 1999-04-19 2000-10-26 Thomson Brandt Gmbh Testverfahren für Schaltungen, die integrierte Schaltkreise enthalten

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483518A (en) * 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US5617420A (en) * 1992-06-17 1997-04-01 Texas Instrument Incorporated Hierarchical connection method, apparatus, and protocol
US5640521A (en) * 1992-06-17 1997-06-17 Texas Instruments Incorporated Addressable shadow port and protocol with remote I/O, contol and interrupt ports
DE69333479T2 (de) * 1992-06-17 2005-03-24 Texas Instruments Inc., Dallas Hierarchisches Verbindungsverfahren und -gerät
US5951703A (en) * 1993-06-28 1999-09-14 Tandem Computers Incorporated System and method for performing improved pseudo-random testing of systems having multi driver buses
US5444716A (en) * 1993-08-30 1995-08-22 At&T Corp. Boundary-scan-based system and method for test and diagnosis
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19917686A1 (de) * 1999-04-19 2000-10-26 Thomson Brandt Gmbh Testverfahren für Schaltungen, die integrierte Schaltkreise enthalten

Also Published As

Publication number Publication date
JPH03240851A (ja) 1991-10-28
DE69031676D1 (de) 1997-12-11
KR100212256B1 (ko) 1999-08-02
EP0417905A2 (de) 1991-03-20
KR910005063A (ko) 1991-03-29
EP0417905B1 (de) 1997-11-05
EP0417905A3 (en) 1992-04-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee