DE69116663T2 - Integrierter Schaltkreis mit Peripherieprüfungssteuerung - Google Patents

Integrierter Schaltkreis mit Peripherieprüfungssteuerung

Info

Publication number
DE69116663T2
DE69116663T2 DE69116663T DE69116663T DE69116663T2 DE 69116663 T2 DE69116663 T2 DE 69116663T2 DE 69116663 T DE69116663 T DE 69116663T DE 69116663 T DE69116663 T DE 69116663T DE 69116663 T2 DE69116663 T2 DE 69116663T2
Authority
DE
Germany
Prior art keywords
integrated circuit
test control
peripheral test
peripheral
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69116663T
Other languages
English (en)
Other versions
DE69116663D1 (de
Inventor
Patrick Lestrat
Regis Leveugle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne e2v Semiconductors SAS
Original Assignee
Thomson SCF Semiconducteurs Specifiques
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson SCF Semiconducteurs Specifiques filed Critical Thomson SCF Semiconducteurs Specifiques
Application granted granted Critical
Publication of DE69116663D1 publication Critical patent/DE69116663D1/de
Publication of DE69116663T2 publication Critical patent/DE69116663T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69116663T 1990-12-07 1991-12-06 Integrierter Schaltkreis mit Peripherieprüfungssteuerung Expired - Fee Related DE69116663T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9015348A FR2670299B1 (fr) 1990-12-07 1990-12-07 Circuit integre avec controleur de test peripherique.

Publications (2)

Publication Number Publication Date
DE69116663D1 DE69116663D1 (de) 1996-03-07
DE69116663T2 true DE69116663T2 (de) 1996-06-05

Family

ID=9403004

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69116663T Expired - Fee Related DE69116663T2 (de) 1990-12-07 1991-12-06 Integrierter Schaltkreis mit Peripherieprüfungssteuerung

Country Status (4)

Country Link
US (1) US5396498A (de)
EP (1) EP0490738B1 (de)
DE (1) DE69116663T2 (de)
FR (1) FR2670299B1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW222725B (en) * 1993-07-09 1994-04-21 Philips Electronics Nv Testing sequential logic circuit upon changing into combinatorial logic circuit
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5920712A (en) * 1994-05-13 1999-07-06 Quickturn Design Systems, Inc. Emulation system having multiple emulator clock cycles per emulated clock cycle
GB9417602D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd A controller for implementing scan testing
US5553236A (en) * 1995-03-03 1996-09-03 Motorola, Inc. Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor
US5606564A (en) * 1995-05-19 1997-02-25 Cirrus Logic Inc. Test logic circuit and method for verifying internal logic of an integrated circuit
US5923865A (en) * 1995-06-28 1999-07-13 Quickturn Design Systems, Inc. Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US5819065A (en) * 1995-06-28 1998-10-06 Quickturn Design Systems, Inc. System and method for emulating memory
US5822564A (en) * 1996-06-03 1998-10-13 Quickturn Design Systems, Inc. Checkpointing in an emulation system
US6804725B1 (en) * 1996-08-30 2004-10-12 Texas Instruments Incorporated IC with state machine controlled linking module
US5900753A (en) * 1997-03-28 1999-05-04 Logicvision, Inc. Asynchronous interface
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6651201B1 (en) * 2000-07-26 2003-11-18 International Business Machines Corporation Programmable memory built-in self-test combining microcode and finite state machine self-test
KR100448706B1 (ko) * 2002-07-23 2004-09-13 삼성전자주식회사 단일 칩 시스템 및 이 시스템의 테스트/디버그 방법
US7809901B2 (en) 2007-08-30 2010-10-05 Micron Technology, Inc. Combined parallel/serial status register read
US7934134B2 (en) * 2008-06-05 2011-04-26 International Business Machines Corporation Method and apparatus for performing logic built-in self-testing of an integrated circuit
US8151149B2 (en) * 2009-06-29 2012-04-03 Hynix Semiconductor Inc. Semiconductor memory apparatus and method of testing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
JPH01132979A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路
US4964148A (en) * 1987-11-30 1990-10-16 Meicor, Inc. Air cooled metal ceramic x-ray tube construction
US5048021A (en) * 1989-08-28 1991-09-10 At&T Bell Laboratories Method and apparatus for generating control signals
US5132973A (en) * 1989-11-06 1992-07-21 Hewlett-Packard Company Testable embedded RAM arrays for bus transaction buffering
US5218680A (en) * 1990-03-15 1993-06-08 International Business Machines Corporation Data link controller with autonomous in tandem pipeline circuit elements relative to network channels for transferring multitasking data in cyclically recurrent time slots
JPH04102353A (ja) * 1990-08-22 1992-04-03 Nec Corp 大規模半導体集積回路
US5230000A (en) * 1991-04-25 1993-07-20 At&T Bell Laboratories Built-in self-test (bist) circuit

Also Published As

Publication number Publication date
FR2670299B1 (fr) 1993-01-22
FR2670299A1 (fr) 1992-06-12
US5396498A (en) 1995-03-07
EP0490738B1 (de) 1996-01-24
EP0490738A1 (de) 1992-06-17
DE69116663D1 (de) 1996-03-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee