DE69026479D1 - Datenprozessor mit Wartezustandsteuerungseinheit - Google Patents
Datenprozessor mit WartezustandsteuerungseinheitInfo
- Publication number
- DE69026479D1 DE69026479D1 DE69026479T DE69026479T DE69026479D1 DE 69026479 D1 DE69026479 D1 DE 69026479D1 DE 69026479 T DE69026479 T DE 69026479T DE 69026479 T DE69026479 T DE 69026479T DE 69026479 D1 DE69026479 D1 DE 69026479D1
- Authority
- DE
- Germany
- Prior art keywords
- control unit
- data processor
- state control
- wait state
- wait
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1310102A JPH03167649A (ja) | 1989-11-28 | 1989-11-28 | ウエイト・サイクル制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69026479D1 true DE69026479D1 (de) | 1996-05-15 |
DE69026479T2 DE69026479T2 (de) | 1996-12-05 |
Family
ID=18001209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69026479T Expired - Fee Related DE69026479T2 (de) | 1989-11-28 | 1990-11-28 | Datenprozessor mit Wartezustandsteuerungseinheit |
Country Status (4)
Country | Link |
---|---|
US (1) | US5201036A (de) |
EP (1) | EP0432575B1 (de) |
JP (1) | JPH03167649A (de) |
DE (1) | DE69026479T2 (de) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04255028A (ja) * | 1991-02-06 | 1992-09-10 | Sharp Corp | マイクロプロセッサ |
EP0913777B1 (de) * | 1991-03-01 | 2005-05-11 | Advanced Micro Devices, Inc. | Ausgangspuffer für Mikroprozessor |
US5339440A (en) * | 1992-08-21 | 1994-08-16 | Hewlett-Packard Co. | Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested |
TW390446U (en) * | 1992-10-01 | 2000-05-11 | Hudson Soft Co Ltd | Information processing system |
JPH06139191A (ja) * | 1992-10-27 | 1994-05-20 | Nec Corp | バスサイクルタイミング制御回路 |
JP3231429B2 (ja) * | 1992-11-06 | 2001-11-19 | 株式会社日立製作所 | 中央処理装置と乗算器とを有する半導体集積回路装置 |
EP0601715A1 (de) * | 1992-12-11 | 1994-06-15 | National Semiconductor Corporation | Für den On-Chip-Speicherzugriff optimierter CPV-Kernbus |
WO1994025914A2 (en) * | 1993-04-30 | 1994-11-10 | Zenith Data Systems Corporation | Symmetric multiprocessing system with unified environment and distributed system functions |
US5444857A (en) * | 1993-05-12 | 1995-08-22 | Intel Corporation | Method and apparatus for cycle tracking variable delay lines |
US5537664A (en) * | 1993-06-30 | 1996-07-16 | Intel Corporation | Methods and apparatus for generating I/O recovery delays in a computer system |
US6038622A (en) * | 1993-09-29 | 2000-03-14 | Texas Instruments Incorporated | Peripheral access with synchronization feature |
JPH08147161A (ja) * | 1994-11-21 | 1996-06-07 | Nec Corp | データ処理装置 |
US5504877A (en) * | 1994-11-29 | 1996-04-02 | Cordata, Inc. | Adaptive DRAM timing set according to sum of capacitance valves retrieved from table based on memory bank size |
US5623648A (en) * | 1995-08-30 | 1997-04-22 | National Semiconductor Corporation | Controller for initiating insertion of wait states on a signal bus |
US5598556A (en) * | 1995-12-07 | 1997-01-28 | Advanced Micro Devices, Inc. | Conditional wait state generator circuit |
US5854944A (en) * | 1996-05-09 | 1998-12-29 | Motorola, Inc. | Method and apparatus for determining wait states on a per cycle basis in a data processing system |
US5857082A (en) * | 1997-04-25 | 1999-01-05 | Intel Corporation | Method and apparatus for quickly transferring data from a first bus to a second bus |
US6067606A (en) * | 1997-12-15 | 2000-05-23 | Intel Corporation | Computer processor with dynamic setting of latency values for memory access |
US6034176A (en) | 1998-03-31 | 2000-03-07 | Teknor Apex Company | Polymer compositions |
GB2339369B (en) * | 1998-07-09 | 2003-06-18 | Advanced Risc Mach Ltd | Apparatus and method for controlling timing of transfer requests within a data processing apparatus |
JP2002091905A (ja) * | 2000-09-20 | 2002-03-29 | Mitsubishi Electric Corp | 半導体装置およびアクセスウェイト数変更プログラムを記録したコンピュータ読み取り可能な記録媒体 |
ITTO20010333A1 (it) * | 2001-04-06 | 2002-10-06 | St Microelectronics Srl | Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile. |
US7075546B2 (en) * | 2003-04-11 | 2006-07-11 | Seiko Epson Corporation | Intelligent wait methodology |
US8004870B2 (en) * | 2009-12-24 | 2011-08-23 | Winbond Electronics Corp. | Memory chips and judgment circuits thereof |
US9405720B2 (en) * | 2013-03-15 | 2016-08-02 | Atmel Corporation | Managing wait states for memory access |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4802120A (en) * | 1984-10-30 | 1989-01-31 | Tandy Corporation | Multistage timing circuit for system bus control |
JPS6353669A (ja) * | 1986-08-22 | 1988-03-07 | Hitachi Micro Comput Eng Ltd | マイクロプロセツサ |
CA1296807C (en) * | 1986-09-08 | 1992-03-03 | Paul R. Culley | Computer system speed control at continuous processor speed |
US4787032A (en) * | 1986-09-08 | 1988-11-22 | Compaq Computer Corporation | Priority arbitration circuit for processor access |
US5151986A (en) * | 1987-08-27 | 1992-09-29 | Motorola, Inc. | Microcomputer with on-board chip selects and programmable bus stretching |
US5032982A (en) * | 1988-05-18 | 1991-07-16 | Zilog, Inc. | Device for timing interrupt acknowledge cycles |
-
1989
- 1989-11-28 JP JP1310102A patent/JPH03167649A/ja active Pending
-
1990
- 1990-11-28 DE DE69026479T patent/DE69026479T2/de not_active Expired - Fee Related
- 1990-11-28 EP EP90122726A patent/EP0432575B1/de not_active Expired - Lifetime
- 1990-11-29 US US07/619,198 patent/US5201036A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH03167649A (ja) | 1991-07-19 |
EP0432575A3 (de) | 1991-07-03 |
EP0432575B1 (de) | 1996-04-10 |
EP0432575A2 (de) | 1991-06-19 |
DE69026479T2 (de) | 1996-12-05 |
US5201036A (en) | 1993-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8339 | Ceased/non-payment of the annual fee |