DE69024461D1 - Halbleiteranordnung mit einem heteroepitaxialen Substrat - Google Patents

Halbleiteranordnung mit einem heteroepitaxialen Substrat

Info

Publication number
DE69024461D1
DE69024461D1 DE69024461T DE69024461T DE69024461D1 DE 69024461 D1 DE69024461 D1 DE 69024461D1 DE 69024461 T DE69024461 T DE 69024461T DE 69024461 T DE69024461 T DE 69024461T DE 69024461 D1 DE69024461 D1 DE 69024461D1
Authority
DE
Germany
Prior art keywords
semiconductor arrangement
heteroepitaxial substrate
heteroepitaxial
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69024461T
Other languages
English (en)
Other versions
DE69024461T2 (de
Inventor
Takashi Eshita
Toshikazu Inoue
Kanetake Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69024461D1 publication Critical patent/DE69024461D1/de
Application granted granted Critical
Publication of DE69024461T2 publication Critical patent/DE69024461T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/928—Active solid-state devices, e.g. transistors, solid-state diodes with shorted PN or schottky junction other than emitter junction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
DE69024461T 1989-10-23 1990-10-23 Halbleiteranordnung mit einem heteroepitaxialen Substrat Expired - Fee Related DE69024461T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1275350A JPH03136319A (ja) 1989-10-23 1989-10-23 ヘテロエピタキシャル基板および半導体装置

Publications (2)

Publication Number Publication Date
DE69024461D1 true DE69024461D1 (de) 1996-02-08
DE69024461T2 DE69024461T2 (de) 1996-05-15

Family

ID=17554251

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69024461T Expired - Fee Related DE69024461T2 (de) 1989-10-23 1990-10-23 Halbleiteranordnung mit einem heteroepitaxialen Substrat

Country Status (4)

Country Link
US (1) US5057880A (de)
EP (1) EP0425244B1 (de)
JP (1) JPH03136319A (de)
DE (1) DE69024461T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021360A (en) * 1989-09-25 1991-06-04 Gte Laboratories Incorporated Method of farbicating highly lattice mismatched quantum well structures
JPH06125141A (ja) * 1992-08-25 1994-05-06 Olympus Optical Co Ltd 半導体量子井戸光学素子
US5523592A (en) * 1993-02-03 1996-06-04 Hitachi, Ltd. Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same
JP2930032B2 (ja) * 1996-09-26 1999-08-03 日本電気株式会社 Ｉｉ−ｖｉ族化合物半導体発光素子およびその製造方法
DE10025264A1 (de) * 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
TWI605552B (zh) * 2016-12-08 2017-11-11 新唐科技股份有限公司 半導體元件、半導體基底及其形成方法
CN115036366A (zh) * 2021-03-05 2022-09-09 联华电子股份有限公司 半导体装置及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4632712A (en) * 1983-09-12 1986-12-30 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
JPH07121720B2 (ja) * 1987-09-28 1995-12-25 株式会社日立製作所 放熱制御器
JP2649936B2 (ja) * 1988-03-01 1997-09-03 富士通株式会社 歪超格子バッファ
JPH02170413A (ja) * 1988-12-22 1990-07-02 Fujitsu Ltd 化合物半導体装置
JP3114809B2 (ja) * 1989-05-31 2000-12-04 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
US5057880A (en) 1991-10-15
EP0425244A2 (de) 1991-05-02
DE69024461T2 (de) 1996-05-15
EP0425244A3 (en) 1991-11-06
JPH03136319A (ja) 1991-06-11
EP0425244B1 (de) 1995-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee