DE69024146D1 - Halbleiteranordnung auf Scheibenskala - Google Patents

Halbleiteranordnung auf Scheibenskala

Info

Publication number
DE69024146D1
DE69024146D1 DE69024146T DE69024146T DE69024146D1 DE 69024146 D1 DE69024146 D1 DE 69024146D1 DE 69024146 T DE69024146 T DE 69024146T DE 69024146 T DE69024146 T DE 69024146T DE 69024146 D1 DE69024146 D1 DE 69024146D1
Authority
DE
Germany
Prior art keywords
semiconductor arrangement
disk scale
disk
scale
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69024146T
Other languages
English (en)
Other versions
DE69024146T2 (de
Inventor
Takaaki Suzuki
Masahiro Tokoro
Yukihiro Nomura
Takeo Tatematsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69024146D1 publication Critical patent/DE69024146D1/de
Application granted granted Critical
Publication of DE69024146T2 publication Critical patent/DE69024146T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
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    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
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    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2924/14Integrated circuits
DE69024146T 1989-09-19 1990-09-17 Halbleiteranordnung auf Scheibenskala Expired - Fee Related DE69024146T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1242674A JP2522837B2 (ja) 1989-09-19 1989-09-19 ウエハ・スケ―ル半導体装置

Publications (2)

Publication Number Publication Date
DE69024146D1 true DE69024146D1 (de) 1996-01-25
DE69024146T2 DE69024146T2 (de) 1996-05-09

Family

ID=17092553

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69024146T Expired - Fee Related DE69024146T2 (de) 1989-09-19 1990-09-17 Halbleiteranordnung auf Scheibenskala

Country Status (4)

Country Link
EP (1) EP0418777B1 (de)
JP (1) JP2522837B2 (de)
KR (1) KR930004252B1 (de)
DE (1) DE69024146T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316976A (en) * 1992-07-08 1994-05-31 National Semiconductor Corporation Crater prevention technique for semiconductor processing
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
JPH06204284A (ja) * 1993-01-08 1994-07-22 Nec Yamagata Ltd 半導体装置
DE69321106T2 (de) * 1993-06-28 1999-02-25 St Microelectronics Srl Integriertes Bauelement mit Mehrschichtmetallisierung und Herstellungsverfahren
EP0637840A1 (de) * 1993-08-05 1995-02-08 AT&T Corp. Integrierte Schaltung mit aktiven Elementen unter den Anschlussflächen
US5965903A (en) * 1995-10-30 1999-10-12 Lucent Technologies Inc. Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein
US5986343A (en) * 1998-05-04 1999-11-16 Lucent Technologies Inc. Bond pad design for integrated circuits

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2247580A1 (de) * 1972-09-28 1974-04-04 Licentia Gmbh Halbleiteranordnung aus einem metallischen kontaktierungsstreifen
JPS5818778A (ja) * 1981-07-24 1983-02-03 Matsushita Electric Ind Co Ltd パタン認識方式
JPS58115860A (ja) * 1981-12-29 1983-07-09 Fujitsu Ltd 半導体装置
JPS5921034A (ja) * 1982-07-27 1984-02-02 Toshiba Corp 半導体装置
JPS59132156A (ja) * 1983-01-17 1984-07-30 Mitsubishi Electric Corp 半導体装置
JPS59222952A (ja) * 1983-06-01 1984-12-14 Toshiba Corp 半導体装置
FR2547112B1 (fr) * 1983-06-03 1986-11-21 Thomson Csf Procede de realisation d'un circuit hybride et circuit hybride logique ou analogique
JPS626267A (ja) * 1985-07-02 1987-01-13 Ricoh Co Ltd 電子写真用キヤリア
GB2177825B (en) * 1985-07-12 1989-07-26 Anamartic Ltd Control system for chained circuit modules
KR900702569A (ko) * 1988-06-01 1990-12-07 원본미기재 웨이퍼스케일 집적회로

Also Published As

Publication number Publication date
KR930004252B1 (ko) 1993-05-22
JP2522837B2 (ja) 1996-08-07
DE69024146T2 (de) 1996-05-09
EP0418777A2 (de) 1991-03-27
JPH03104247A (ja) 1991-05-01
EP0418777B1 (de) 1995-12-13
EP0418777A3 (en) 1991-07-31

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