KR900702569A - 웨이퍼스케일 집적회로 - Google Patents
웨이퍼스케일 집적회로Info
- Publication number
- KR900702569A KR900702569A KR1019900700196A KR900700196A KR900702569A KR 900702569 A KR900702569 A KR 900702569A KR 1019900700196 A KR1019900700196 A KR 1019900700196A KR 900700196 A KR900700196 A KR 900700196A KR 900702569 A KR900702569 A KR 900702569A
- Authority
- KR
- South Korea
- Prior art keywords
- wafer
- integrated circuit
- modules
- scale integrated
- band
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 몇몇 접속상태를 나타내는 1쌍의 칩 도면, 제2도는 다른 접속상태를 나타내는 칩의 도면, 제3도는 단순화한 칩의 블록도.
Claims (10)
- 한 웨이퍼상에 형성된 집적회로의 어레이와, 모든 모듈로 연장되는 신호선 및 전원공급선을 포함하는 모듈 및 대역선로간에 설치되는 국부접속부를 구비하여 구성되고, 각 모듈 또는 모듈의 클러스터가 전원공급 본드패드를 갖추고 있으며, 전원공급선이 상기 본드패드에 결속되는 본드와이어 스티치에 의해 형성된 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 제1항에 있어서, 본드와이어가 웨이퍼의 2곳의 반대편 가장자리로 부터 웨이퍼내로 병렬로 연장되고 중간지점에서 각각 차단되는 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 한 웨이퍼상에 형성된 집적회로의 어레이와, 모든 모듈로 연장되는 신호선 및 전원공급선을 포함하는 모듈 및 대역선로간에 설치되는 국부접속부를 포함하여 구성되고, 적어도 몇몇의 대역선호가 웨이퍼의 2곳의 반대측으로 부터 웨이터내로 서로 만나지 않고 연장됨으로써, 한쪽에서 연장된 선로의 결함이 다른 쪽에서 연장된 상대선로에 영향을 끼치지 않도록 된 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 제3항에 있어서,적어도 몇몇의 대역선로가 금속을 함유하지 않는 중앙밴드에 의해 차단되는 금속층내에 형성된 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 제4항에 있어서, 금속층의 패턴이 하나의 모듈이나 모듈의 클러스터에 속하는 단일의 스탭퍼 망선을 사용하여 규정되고, 중앙밴드가 전반적인 웨이퍼설계마스크를 사용하여 분리적으로 규정되도록 된 것을 특징으로 하는 웨이퍼스케일 집적회로의 제조방법.
- 제4항에 있어서, 금속층의 패턴이 하나의 모듈이나 모듈의 클러스터에 속하는 단일의 스탭퍼 망선을 사용하여 규정되고, 중앙밴드는 금속과 무관하게 선로가 다른 내부 행 밴드를 연속해서 가로지르도록 하는 방식으로 망선을 고름으로써 규정되는 것을 특징으로 하는 웨이퍼스케일 집적회로의 제조방법
- 제4항에 있어서, 금속층의 패턴이 중앙밴드를 측면에 접하는 모듈에 대해 제1스탭퍼 망선을 사용하고 다른 모듈에 대해 다른 스텝퍼 망선을 사용함으로써 규정되는 것을 특징으로 하는 웨이퍼스케일 집적회로의 제조방법.
- 한 웨이퍼상에 형성되는 집적회로의 어레이와, 모든 모듈로 연장되는 신호선 및 전원공급선을 포함하는 대역선로와 모듈간에 설치된 국부접속부를 구비하여 구성되고, 각 모듈 또는 모듈의 클러스터에서 다수의 신호선이 대응되는 분드패드로 연장되어, 본드 와이어 접속부가 소망하는 임의의 장소에, 특히 웨이퍼의 가장자리에서 소망하는 임의의 장소로 만들어지는 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 제8항에 있어서, 신호선이 적어도 데이터용 입력, 출력선을 포함하고서 분드패드로 연장되는 것을 특징으로 하는 웨이퍼스케일 집적회로.
- 첨부된 도면 제1도∼제5도 또는 제6도를 참조하여 설명된 구성의 웨이퍼스케일 집적회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63132589A JP2516403B2 (ja) | 1988-06-01 | 1988-06-01 | ウエハ・スケ―ル・メモリ |
JP63/132589 | 1988-06-01 | ||
GB888828482A GB8828482D0 (en) | 1988-12-06 | 1988-12-06 | Wafer scale integrated circuits |
GB8828482.3 | 1988-12-06 | ||
PCT/GB1989/000594 WO1989012320A1 (en) | 1988-06-01 | 1989-05-31 | Wafer scale integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
KR900702569A true KR900702569A (ko) | 1990-12-07 |
Family
ID=26294706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900700196A KR900702569A (ko) | 1988-06-01 | 1989-05-31 | 웨이퍼스케일 집적회로 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0378613A1 (ko) |
KR (1) | KR900702569A (ko) |
WO (1) | WO1989012320A1 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2522837B2 (ja) * | 1989-09-19 | 1996-08-07 | 富士通株式会社 | ウエハ・スケ―ル半導体装置 |
JPH03106029A (ja) * | 1989-09-20 | 1991-05-02 | Fujitsu Ltd | ウエハ・スケール・ic |
US5128737A (en) * | 1990-03-02 | 1992-07-07 | Silicon Dynamics, Inc. | Semiconductor integrated circuit fabrication yield improvements |
GB9305801D0 (en) * | 1993-03-19 | 1993-05-05 | Deans Alexander R | Semiconductor memory system |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2547112B1 (fr) * | 1983-06-03 | 1986-11-21 | Thomson Csf | Procede de realisation d'un circuit hybride et circuit hybride logique ou analogique |
GB2177825B (en) * | 1985-07-12 | 1989-07-26 | Anamartic Ltd | Control system for chained circuit modules |
JPH0693497B2 (ja) * | 1986-07-30 | 1994-11-16 | 日本電気株式会社 | 相補型mis集積回路 |
-
1989
- 1989-05-31 WO PCT/GB1989/000594 patent/WO1989012320A1/en not_active Application Discontinuation
- 1989-05-31 EP EP89906418A patent/EP0378613A1/en not_active Withdrawn
- 1989-05-31 KR KR1019900700196A patent/KR900702569A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
EP0378613A1 (en) | 1990-07-25 |
WO1989012320A1 (en) | 1989-12-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |