DE69021704D1 - Vorladeschaltung für Speicherbus. - Google Patents

Vorladeschaltung für Speicherbus.

Info

Publication number
DE69021704D1
DE69021704D1 DE69021704T DE69021704T DE69021704D1 DE 69021704 D1 DE69021704 D1 DE 69021704D1 DE 69021704 T DE69021704 T DE 69021704T DE 69021704 T DE69021704 T DE 69021704T DE 69021704 D1 DE69021704 D1 DE 69021704D1
Authority
DE
Germany
Prior art keywords
memory bus
precharge circuit
precharge
circuit
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021704T
Other languages
English (en)
Other versions
DE69021704T2 (de
Inventor
Patrice Brossard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Publication of DE69021704D1 publication Critical patent/DE69021704D1/de
Application granted granted Critical
Publication of DE69021704T2 publication Critical patent/DE69021704T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
DE69021704T 1989-12-21 1990-12-07 Vorladeschaltung für Speicherbus. Expired - Fee Related DE69021704T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8916954A FR2656455B1 (fr) 1989-12-21 1989-12-21 Circuit de precharge d'un bus de memoire.

Publications (2)

Publication Number Publication Date
DE69021704D1 true DE69021704D1 (de) 1995-09-21
DE69021704T2 DE69021704T2 (de) 1996-02-29

Family

ID=9388797

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021704T Expired - Fee Related DE69021704T2 (de) 1989-12-21 1990-12-07 Vorladeschaltung für Speicherbus.

Country Status (6)

Country Link
US (1) US5243571A (de)
EP (1) EP0434495B1 (de)
JP (1) JPH07101556B2 (de)
DE (1) DE69021704T2 (de)
ES (1) ES2078328T3 (de)
FR (1) FR2656455B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2771729B2 (ja) * 1992-04-16 1998-07-02 三菱電機株式会社 チャージポンプ回路
JP2801824B2 (ja) * 1992-12-28 1998-09-21 株式会社東芝 半導体集積回路装置
SG48335A1 (en) * 1993-04-19 1998-04-17 Koninkl Philips Electronics Nv Bicmos output driver circuit
US5495191A (en) * 1994-03-25 1996-02-27 Sun Microsystems, Inc. Single ended dynamic sense amplifier
US5629634A (en) * 1995-08-21 1997-05-13 International Business Machines Corporation Low-power, tristate, off-chip driver circuit
KR100452176B1 (ko) * 1995-11-30 2005-01-05 코닌클리케 필립스 일렉트로닉스 엔.브이. 전류원-숏회로
JP3210567B2 (ja) * 1996-03-08 2001-09-17 株式会社東芝 半導体出力回路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208730A (en) * 1978-08-07 1980-06-17 Rca Corporation Precharge circuit for memory array
GB2070372B (en) * 1980-01-31 1983-09-28 Tokyo Shibaura Electric Co Semiconductor memory device
JPS5925423A (ja) * 1982-08-04 1984-02-09 Hitachi Ltd 半導体装置
JPS60125998A (ja) * 1983-12-12 1985-07-05 Fujitsu Ltd 半導体記憶装置
JPS60163295A (ja) * 1984-02-03 1985-08-26 Hitachi Ltd 半導体記憶装置
JP2544343B2 (ja) * 1985-02-07 1996-10-16 株式会社日立製作所 半導体集積回路装置
US4873673A (en) * 1986-12-03 1989-10-10 Hitachi, Ltd. Driver circuit having a current mirror circuit
JPH0810556B2 (ja) * 1986-04-17 1996-01-31 株式会社日立製作所 半導体メモリ回路
JPS6369096A (ja) * 1986-09-10 1988-03-29 Sony Corp プリチヤ−ジ回路
US5058067A (en) * 1990-06-06 1991-10-15 National Semiconductor Corporation Individual bit line recovery circuits
US5103113A (en) * 1990-06-13 1992-04-07 Texas Instruments Incorporated Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal
US5070261A (en) * 1990-12-04 1991-12-03 Texas Instruments Incorporated Apparatus and method for translating voltages

Also Published As

Publication number Publication date
JPH07101556B2 (ja) 1995-11-01
ES2078328T3 (es) 1995-12-16
EP0434495A1 (de) 1991-06-26
EP0434495B1 (de) 1995-08-16
JPH04212783A (ja) 1992-08-04
DE69021704T2 (de) 1996-02-29
US5243571A (en) 1993-09-07
FR2656455A1 (fr) 1991-06-28
FR2656455B1 (fr) 1992-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee