DE69014347T2 - Feinstruktur-Litographieverfahren unter Verwendung von Fotolackschichten und einer plattierten Transferschicht. - Google Patents

Feinstruktur-Litographieverfahren unter Verwendung von Fotolackschichten und einer plattierten Transferschicht.

Info

Publication number
DE69014347T2
DE69014347T2 DE69014347T DE69014347T DE69014347T2 DE 69014347 T2 DE69014347 T2 DE 69014347T2 DE 69014347 T DE69014347 T DE 69014347T DE 69014347 T DE69014347 T DE 69014347T DE 69014347 T2 DE69014347 T2 DE 69014347T2
Authority
DE
Germany
Prior art keywords
transfer layer
fine structure
lithography process
photoresist layers
plated transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69014347T
Other languages
English (en)
Other versions
DE69014347D1 (de
Inventor
Lawrence G Studebaker
Edward H Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69014347D1 publication Critical patent/DE69014347D1/de
Publication of DE69014347T2 publication Critical patent/DE69014347T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/10—Lift-off masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Electron Beam Exposure (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
DE69014347T 1989-02-24 1990-01-24 Feinstruktur-Litographieverfahren unter Verwendung von Fotolackschichten und einer plattierten Transferschicht. Expired - Fee Related DE69014347T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/315,351 US5091342A (en) 1989-02-24 1989-02-24 Multilevel resist plated transfer layer process for fine line lithography

Publications (2)

Publication Number Publication Date
DE69014347D1 DE69014347D1 (de) 1995-01-12
DE69014347T2 true DE69014347T2 (de) 1995-06-01

Family

ID=23224005

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69014347T Expired - Fee Related DE69014347T2 (de) 1989-02-24 1990-01-24 Feinstruktur-Litographieverfahren unter Verwendung von Fotolackschichten und einer plattierten Transferschicht.

Country Status (4)

Country Link
US (1) US5091342A (de)
EP (1) EP0384145B1 (de)
JP (1) JP3041625B2 (de)
DE (1) DE69014347T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342481A (en) * 1991-02-15 1994-08-30 Sony Corporation Dry etching method
KR950027933A (ko) * 1994-03-21 1995-10-18 김주용 위상반전 마스크
IT1271298B (it) * 1994-12-20 1997-05-27 Alcatel Italia Processo fotolitografico per contatto per la realizzazione di linee metalliche su un substrato
US5834159A (en) * 1996-04-22 1998-11-10 Advanced Micro Devices, Inc. Image reversal technique for forming small structures in integrated circuits
KR100490575B1 (ko) * 2001-08-03 2005-05-17 야마하 가부시키가이샤 귀금속 박막 패턴 형성방법
US7229745B2 (en) * 2004-06-14 2007-06-12 Bae Systems Information And Electronic Systems Integration Inc. Lithographic semiconductor manufacturing using a multi-layered process
JP2008511980A (ja) * 2004-08-31 2008-04-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 層構造に多段リセスを形成する方法、及び多段リセスゲートを具備した電界効果トランジスタ
US7224258B2 (en) * 2004-09-27 2007-05-29 Ohmcraft, Inc. Fine line thick film resistors by photolithography
KR100684271B1 (ko) * 2005-03-11 2007-02-20 한국표준과학연구원 금속, 반도체, 절연체 패턴의 선폭과 크기를 줄이는 방법
KR100738056B1 (ko) * 2005-05-18 2007-07-12 삼성에스디아이 주식회사 Ｆｅｄ의 제조방법
US20070134943A2 (en) * 2006-04-02 2007-06-14 Dunnrowicz Clarence J Subtractive - Additive Edge Defined Lithography

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4165395A (en) * 1977-06-30 1979-08-21 International Business Machines Corporation Process for forming a high aspect ratio structure by successive exposures with electron beam and actinic radiation
US4266333A (en) * 1979-04-27 1981-05-12 Rca Corporation Method of making a Schottky barrier field effect transistor
US4376664A (en) * 1979-05-31 1983-03-15 Fujitsu Limited Method of producing a semiconductor device
JPS59141222A (ja) * 1983-01-31 1984-08-13 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4532002A (en) * 1984-04-10 1985-07-30 Rca Corporation Multilayer planarizing structure for lift-off technique

Also Published As

Publication number Publication date
EP0384145A1 (de) 1990-08-29
JPH02251129A (ja) 1990-10-08
US5091342A (en) 1992-02-25
DE69014347D1 (de) 1995-01-12
EP0384145B1 (de) 1994-11-30
JP3041625B2 (ja) 2000-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8339 Ceased/non-payment of the annual fee