DE69300907D1 - Keramisches Mehrschichtsubstrat mit Gradienten-Kontaktlöchern. - Google Patents

Keramisches Mehrschichtsubstrat mit Gradienten-Kontaktlöchern.

Info

Publication number
DE69300907D1
DE69300907D1 DE69300907T DE69300907T DE69300907D1 DE 69300907 D1 DE69300907 D1 DE 69300907D1 DE 69300907 T DE69300907 T DE 69300907T DE 69300907 T DE69300907 T DE 69300907T DE 69300907 D1 DE69300907 D1 DE 69300907D1
Authority
DE
Germany
Prior art keywords
contact holes
multilayer substrate
ceramic multilayer
gradient contact
gradient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69300907T
Other languages
English (en)
Other versions
DE69300907T2 (de
Inventor
John Ulrich Knickerbocker
Charles Hampton Perry
Donald Rene Wall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69300907D1 publication Critical patent/DE69300907D1/de
Application granted granted Critical
Publication of DE69300907T2 publication Critical patent/DE69300907T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0269—Non-uniform distribution or concentration of particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE69300907T 1992-09-23 1993-08-24 Keramisches Mehrschichtsubstrat mit Gradienten-Kontaktlöchern. Expired - Fee Related DE69300907T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/949,595 US5260519A (en) 1992-09-23 1992-09-23 Multilayer ceramic substrate with graded vias

Publications (2)

Publication Number Publication Date
DE69300907D1 true DE69300907D1 (de) 1996-01-11
DE69300907T2 DE69300907T2 (de) 1996-06-20

Family

ID=25489303

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69300907T Expired - Fee Related DE69300907T2 (de) 1992-09-23 1993-08-24 Keramisches Mehrschichtsubstrat mit Gradienten-Kontaktlöchern.

Country Status (4)

Country Link
US (1) US5260519A (de)
EP (1) EP0589813B1 (de)
JP (1) JPH0834351B2 (de)
DE (1) DE69300907T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371327A (en) * 1992-02-19 1994-12-06 Shin-Etsu Polymer Co., Ltd. Heat-sealable connector sheet
DE4318339A1 (de) * 1993-06-02 1994-12-08 Philips Patentverwaltung Verschlossene Durchkontaktierung für ein Keramiksubstrat einer Dickschichtschaltung und ein Verfahren zur Herstellung derselben
US5834824A (en) 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5808351A (en) 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5813881A (en) 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5917229A (en) 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5552232A (en) * 1994-12-21 1996-09-03 International Business Machines Corporation Aluminum nitride body having graded metallurgy
US5962815A (en) 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
JP3290041B2 (ja) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層プリント基板、多層プリント基板の製造方法
US5906042A (en) 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5767575A (en) 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US5872338A (en) 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5787578A (en) * 1996-07-09 1998-08-04 International Business Machines Corporation Method of selectively depositing a metallic layer on a ceramic substrate
US6034427A (en) 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6376054B1 (en) * 1999-02-10 2002-04-23 International Business Machines Corporation Surface metallization structure for multiple chip test and burn-in
US6136419A (en) * 1999-05-26 2000-10-24 International Business Machines Corporation Ceramic substrate having a sealed layer
US6900395B2 (en) * 2002-11-26 2005-05-31 International Business Machines Corporation Enhanced high-frequency via interconnection for improved reliability
JP5142824B2 (ja) * 2008-05-28 2013-02-13 京セラ株式会社 配線基板およびその製造方法
JP5164670B2 (ja) * 2008-05-28 2013-03-21 京セラ株式会社 配線基板およびその製造方法
JP5501745B2 (ja) * 2009-12-01 2014-05-28 株式会社ニデック 視覚再生補助装置
US9337060B1 (en) * 2011-11-01 2016-05-10 Triton Microtechnologies Filling materials and methods of filling through holes for improved adhesion and hermeticity in glass substrates and other electronic components
US9374892B1 (en) * 2011-11-01 2016-06-21 Triton Microtechnologies Filling materials and methods of filling through holes for improved adhesion and hermeticity in glass substrates and other electronic components
US9236274B1 (en) * 2011-11-01 2016-01-12 Triton Microtechnologies Filling materials and methods of filling through holes for improved adhesion and hermeticity in glass substrates and other electronic components
KR101483875B1 (ko) * 2013-07-31 2015-01-16 삼성전기주식회사 글라스 코어기판 및 그 제조방법
US9232645B2 (en) 2013-11-22 2016-01-05 International Business Machines Corporation High speed differential wiring in glass ceramic MCMS
US10010396B2 (en) * 2014-03-19 2018-07-03 Second Sight Medical Products, Inc. Multilayer composite materials vias
CN104064478B (zh) * 2014-06-24 2016-08-31 南京航空航天大学 一种铜/氮化铝陶瓷复合导热基板的制作方法
US20230005834A1 (en) * 2014-08-18 2023-01-05 Samtec, Inc. Electrically conductive vias and methods for producing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4301324A (en) * 1978-02-06 1981-11-17 International Business Machines Corporation Glass-ceramic structures and sintered multilayer substrates thereof with circuit patterns of gold, silver or copper
US4234367A (en) * 1979-03-23 1980-11-18 International Business Machines Corporation Method of making multilayered glass-ceramic structures having an internal distribution of copper-based conductors
US4594181A (en) * 1984-09-17 1986-06-10 E. I. Du Pont De Nemours And Company Metal oxide-coated copper powder
DE68912932T2 (de) * 1989-05-12 1994-08-11 Ibm Deutschland Glas-Keramik-Gegenstand und Verfahren zu dessen Herstellung.
JP2665561B2 (ja) * 1989-09-26 1997-10-22 日本特殊陶業株式会社 セラミック多層基板
US5073180A (en) * 1991-03-20 1991-12-17 International Business Machines Corporation Method for forming sealed co-fired glass ceramic structures

Also Published As

Publication number Publication date
JPH06196864A (ja) 1994-07-15
JPH0834351B2 (ja) 1996-03-29
EP0589813A1 (de) 1994-03-30
DE69300907T2 (de) 1996-06-20
US5260519A (en) 1993-11-09
EP0589813B1 (de) 1995-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee