DE68928113D1 - Reihenfolgesteuersystem zur Behandlung von Befehlen - Google Patents

Reihenfolgesteuersystem zur Behandlung von Befehlen

Info

Publication number
DE68928113D1
DE68928113D1 DE68928113T DE68928113T DE68928113D1 DE 68928113 D1 DE68928113 D1 DE 68928113D1 DE 68928113 T DE68928113 T DE 68928113T DE 68928113 T DE68928113 T DE 68928113T DE 68928113 D1 DE68928113 D1 DE 68928113D1
Authority
DE
Germany
Prior art keywords
control system
sequence control
handling commands
commands
handling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68928113T
Other languages
English (en)
Other versions
DE68928113T2 (de
Inventor
Naoki C O Nec Corporatio Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE68928113D1 publication Critical patent/DE68928113D1/de
Application granted granted Critical
Publication of DE68928113T2 publication Critical patent/DE68928113T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G06F15/8084—Special arrangements thereof, e.g. mask or switch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
DE68928113T 1988-04-01 1989-03-31 Reihenfolgesteuersystem zur Behandlung von Befehlen Expired - Lifetime DE68928113T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8151988 1988-04-01

Publications (2)

Publication Number Publication Date
DE68928113D1 true DE68928113D1 (de) 1997-07-17
DE68928113T2 DE68928113T2 (de) 1997-10-09

Family

ID=13748593

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928113T Expired - Lifetime DE68928113T2 (de) 1988-04-01 1989-03-31 Reihenfolgesteuersystem zur Behandlung von Befehlen

Country Status (4)

Country Link
US (2) US5241633A (de)
EP (1) EP0340453B1 (de)
AU (1) AU615043B2 (de)
DE (1) DE68928113T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
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EP0340453B1 (de) * 1988-04-01 1997-06-11 Nec Corporation Reihenfolgesteuersystem zur Behandlung von Befehlen
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5623650A (en) * 1989-12-29 1997-04-22 Cray Research, Inc. Method of processing a sequence of conditional vector IF statements
US5544337A (en) * 1989-12-29 1996-08-06 Cray Research, Inc. Vector processor having registers for control by vector resisters
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
US5488729A (en) * 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
JPH06110688A (ja) * 1991-06-13 1994-04-22 Internatl Business Mach Corp <Ibm> 複数の順序外れ命令を並行処理するためのコンピュータ・システム
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
JP3105197B2 (ja) 1991-06-24 2000-10-30 株式会社日立製作所 除算回路及び除算方法
JP2984463B2 (ja) 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
US5404557A (en) * 1991-11-22 1995-04-04 Matsushita Electric Industrial Co., Ltd. Data processor with plural instruction execution parts for synchronized parallel processing and exception handling
US5619662A (en) * 1992-11-12 1997-04-08 Digital Equipment Corporation Memory reference tagging
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5875337A (en) * 1995-09-14 1999-02-23 Nec Corporation Modifier for a program executing parallel processes that reduces wait time for access to a shared resource
US5751983A (en) * 1995-10-03 1998-05-12 Abramson; Jeffrey M. Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
US5848256A (en) * 1996-09-30 1998-12-08 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for address disambiguation using address component identifiers
US5963723A (en) * 1997-03-26 1999-10-05 International Business Machines Corporation System for pairing dependent instructions having non-contiguous addresses during dispatch
US6094713A (en) * 1997-09-30 2000-07-25 Intel Corporation Method and apparatus for detecting address range overlaps
JP4001461B2 (ja) * 1999-01-25 2007-10-31 三菱電機株式会社 プログラマブルコントローラの周辺装置
US6701424B1 (en) * 2000-04-07 2004-03-02 Nintendo Co., Ltd. Method and apparatus for efficient loading and storing of vectors
JP3733842B2 (ja) * 2000-07-12 2006-01-11 日本電気株式会社 ベクトルスキャタ命令制御回路及びベクトル型情報処理装置
JP3734032B2 (ja) * 2002-07-25 2006-01-11 日本電気株式会社 情報処理装置及びそのメモリ制御方法
US8181001B2 (en) * 2008-09-24 2012-05-15 Apple Inc. Conditional data-dependency resolution in vector processors
US8176299B2 (en) * 2008-09-24 2012-05-08 Apple Inc. Generating stop indicators based on conditional data dependency in vector processors
US8160242B2 (en) * 2008-10-07 2012-04-17 Lsi Corporation Efficient implementation of arithmetical secure hash techniques
US8688957B2 (en) 2010-12-21 2014-04-01 Intel Corporation Mechanism for conflict detection using SIMD
US9021233B2 (en) 2011-09-28 2015-04-28 Arm Limited Interleaving data accesses issued in response to vector access instructions
US20130173886A1 (en) * 2012-01-04 2013-07-04 Qualcomm Incorporated Processor with Hazard Tracking Employing Register Range Compares
US9411584B2 (en) 2012-12-29 2016-08-09 Intel Corporation Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality
US9411592B2 (en) 2012-12-29 2016-08-09 Intel Corporation Vector address conflict resolution with vector population count functionality
US9715386B2 (en) 2014-09-29 2017-07-25 Apple Inc. Conditional stop instruction with accurate dependency detection

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
JPS57193842A (en) * 1981-05-22 1982-11-29 Hitachi Ltd Request conflict detecting system
JPS6069746A (ja) * 1983-09-26 1985-04-20 Fujitsu Ltd ベクトル・デ−タ処理装置の制御方式
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPS60156151A (ja) * 1983-12-23 1985-08-16 Nec Corp メモリアクセス制御装置
EP0184791A1 (de) * 1984-12-07 1986-06-18 Nec Corporation Informationsverarbeitungsgerät zur schnellen Verarbeitung von Befehlen aus verschiedenen Gruppen
US4972314A (en) * 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4873630A (en) * 1985-07-31 1989-10-10 Unisys Corporation Scientific processor to support a host processor referencing common memory
US4789925A (en) * 1985-07-31 1988-12-06 Unisys Corporation Vector data logical usage conflict detection
US4847754A (en) * 1985-10-15 1989-07-11 International Business Machines Corporation Extended atomic operations
JPS62115571A (ja) * 1985-11-15 1987-05-27 Fujitsu Ltd ベクトルアクセス制御方式
US4760518A (en) * 1986-02-28 1988-07-26 Scientific Computer Systems Corporation Bi-directional databus system for supporting superposition of vector and scalar operations in a computer
US4866598A (en) * 1986-10-31 1989-09-12 Ncr Corporation Communications base microcontroller
JPH01145770A (ja) * 1987-12-01 1989-06-07 Hitachi Ltd ベクトル処理装置
EP0340453B1 (de) * 1988-04-01 1997-06-11 Nec Corporation Reihenfolgesteuersystem zur Behandlung von Befehlen
US4893233A (en) * 1988-04-18 1990-01-09 Motorola, Inc. Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit
US4903264A (en) * 1988-04-18 1990-02-20 Motorola, Inc. Method and apparatus for handling out of order exceptions in a pipelined data unit

Also Published As

Publication number Publication date
EP0340453B1 (de) 1997-06-11
US5349692A (en) 1994-09-20
EP0340453A3 (de) 1992-01-29
US5241633A (en) 1993-08-31
EP0340453A2 (de) 1989-11-08
AU3238589A (en) 1989-10-05
AU615043B2 (en) 1991-09-19
DE68928113T2 (de) 1997-10-09

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Legal Events

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