DE68927192D1 - Halbleiteranordnung mit Gattermatrix - Google Patents

Halbleiteranordnung mit Gattermatrix

Info

Publication number
DE68927192D1
DE68927192D1 DE68927192T DE68927192T DE68927192D1 DE 68927192 D1 DE68927192 D1 DE 68927192D1 DE 68927192 T DE68927192 T DE 68927192T DE 68927192 T DE68927192 T DE 68927192T DE 68927192 D1 DE68927192 D1 DE 68927192D1
Authority
DE
Germany
Prior art keywords
semiconductor device
gate matrix
matrix
gate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927192T
Other languages
English (en)
Other versions
DE68927192T2 (de
Inventor
Hiroyuki Hara
Yasuhiro Sugimoto
Tetsu Nagamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68927192D1 publication Critical patent/DE68927192D1/de
Publication of DE68927192T2 publication Critical patent/DE68927192T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE68927192T 1988-02-19 1989-02-17 Halbleiteranordnung mit Gattermatrix Expired - Fee Related DE68927192T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63035171A JPH0831581B2 (ja) 1988-02-19 1988-02-19 半導体装置

Publications (2)

Publication Number Publication Date
DE68927192D1 true DE68927192D1 (de) 1996-10-24
DE68927192T2 DE68927192T2 (de) 1997-03-06

Family

ID=12434410

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927192T Expired - Fee Related DE68927192T2 (de) 1988-02-19 1989-02-17 Halbleiteranordnung mit Gattermatrix

Country Status (5)

Country Link
US (1) US5066996A (de)
EP (1) EP0329152B1 (de)
JP (1) JPH0831581B2 (de)
KR (1) KR920006750B1 (de)
DE (1) DE68927192T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4002780C2 (de) * 1990-01-31 1995-01-19 Fraunhofer Ges Forschung Basiszelle für eine kanallose Gate-Array-Anordnung
EP0457150A3 (en) * 1990-05-14 1992-06-17 Lsi Logic Corporation Bicmos compacted logic array
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
JP2505910B2 (ja) * 1990-05-24 1996-06-12 株式会社東芝 半導体集積回路用セルライブラリ
JP2714996B2 (ja) * 1990-08-08 1998-02-16 三菱電機株式会社 半導体集積回路装置
JPH04103161A (ja) * 1990-08-22 1992-04-06 Toshiba Corp バイポーラトランジスタ・絶縁ゲート型トランジスタ混載半導体装置
US5764085A (en) * 1996-02-28 1998-06-09 Hewlett-Packard Company Method and apparatus for sharing a fet between a plurality of operationally exclusive logic gates
CN104094403B (zh) * 2011-12-23 2017-03-22 英特尔公司 具有使用者可选值的工艺可调式电阻器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58112343A (ja) * 1981-12-26 1983-07-04 Olympus Optical Co Ltd 半導体装置およびその製造方法
JPS59177944A (ja) * 1983-03-28 1984-10-08 Hitachi Ltd 半導体集積回路装置
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS60179042U (ja) * 1984-05-09 1985-11-28 シャープ株式会社 ゲ−トアレイ半導体装置
JPS61100947A (ja) * 1984-10-22 1986-05-19 Toshiba Corp 半導体集積回路装置
JPH0815209B2 (ja) * 1985-01-25 1996-02-14 株式会社日立製作所 半導体集積回路装置
CN1003549B (zh) * 1985-01-25 1989-03-08 株式会社日立制作所 半导体集成电路器件

Also Published As

Publication number Publication date
JPH0831581B2 (ja) 1996-03-27
DE68927192T2 (de) 1997-03-06
EP0329152B1 (de) 1996-09-18
KR890013771A (ko) 1989-09-26
JPH01211945A (ja) 1989-08-25
EP0329152A2 (de) 1989-08-23
US5066996A (en) 1991-11-19
KR920006750B1 (ko) 1992-08-17
EP0329152A3 (de) 1991-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee