DE68924637D1 - Speicheranordnung für Mehrprozessorsysteme. - Google Patents

Speicheranordnung für Mehrprozessorsysteme.

Info

Publication number
DE68924637D1
DE68924637D1 DE68924637T DE68924637T DE68924637D1 DE 68924637 D1 DE68924637 D1 DE 68924637D1 DE 68924637 T DE68924637 T DE 68924637T DE 68924637 T DE68924637 T DE 68924637T DE 68924637 D1 DE68924637 D1 DE 68924637D1
Authority
DE
Germany
Prior art keywords
cells
multiprocessor systems
memory arrangement
ram
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924637T
Other languages
English (en)
Other versions
DE68924637T2 (de
Inventor
Leonard John Umina
Robert Anthony Anselmo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68924637D1 publication Critical patent/DE68924637D1/de
Application granted granted Critical
Publication of DE68924637T2 publication Critical patent/DE68924637T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
DE68924637T 1988-12-22 1989-07-03 Speicheranordnung für Mehrprozessorsysteme. Expired - Fee Related DE68924637T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/288,168 US5031146A (en) 1988-12-22 1988-12-22 Memory apparatus for multiple processor systems

Publications (2)

Publication Number Publication Date
DE68924637D1 true DE68924637D1 (de) 1995-11-30
DE68924637T2 DE68924637T2 (de) 1996-06-13

Family

ID=23106033

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924637T Expired - Fee Related DE68924637T2 (de) 1988-12-22 1989-07-03 Speicheranordnung für Mehrprozessorsysteme.

Country Status (5)

Country Link
US (1) US5031146A (de)
EP (1) EP0375105B1 (de)
JP (1) JPH02259866A (de)
AT (1) ATE129593T1 (de)
DE (1) DE68924637T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3321802B2 (ja) * 1990-06-28 2002-09-09 キヤノン株式会社 ディジタル信号処理装置
US5053996A (en) * 1991-02-26 1991-10-01 Sgs-Thomson Microelectronics, Inc. Dual state memory storage cell with improved data transfer circuitry
JPH04307495A (ja) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp 半導体記憶装置
US5404455A (en) * 1991-12-31 1995-04-04 Dictaphone Corporation Time division multiplexer chip for supporting alternating communication between a pair of RAMs and two different interfaces
US5359557A (en) * 1992-12-04 1994-10-25 International Business Machines Corporation Dual-port array with storage redundancy having a cross-write operation
US5436863A (en) * 1993-04-26 1995-07-25 Nec Corporation Semiconductor memory device
JPH07201191A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 不揮発性半導体メモリ装置
US6775372B1 (en) 1999-06-02 2004-08-10 Dictaphone Corporation System and method for multi-stage data logging
US6246752B1 (en) 1999-06-08 2001-06-12 Valerie Bscheider System and method for data recording
US6252946B1 (en) 1999-06-08 2001-06-26 David A. Glowny System and method for integrating call record information
US6252947B1 (en) * 1999-06-08 2001-06-26 David A. Diamond System and method for data recording and playback
US6249570B1 (en) 1999-06-08 2001-06-19 David A. Glowny System and method for recording and storing telephone call information
JP2003015954A (ja) * 2001-06-28 2003-01-17 Sharp Corp 半導体記憶装置および情報機器、半導体記憶装置のアクセス期間設定方法
KR100609623B1 (ko) * 2005-02-16 2006-08-08 삼성전자주식회사 내부 메모리 디바이스간의 직접적 데이터 이동이 가능한 복합 메모리 칩 및 데이터 이동방법
CA2551045C (en) * 2005-06-30 2008-04-22 Hitachi, Ltd. Input-output control apparatus, input-output control method, process control apparatus and process control method
US20090006742A1 (en) * 2007-06-27 2009-01-01 Min Huang Method and apparatus improving performance of a digital memory array device
US8238140B2 (en) * 2008-01-07 2012-08-07 The New Industry Research Organization Semiconductor memory and program
JP5298373B2 (ja) * 2009-01-04 2013-09-25 国立大学法人神戸大学 半導体メモリのハーフセレクト防止セル配置
JP5256534B2 (ja) * 2009-03-30 2013-08-07 国立大学法人神戸大学 半導体メモリのメモリセル間のデータコピー方法
JP5311309B2 (ja) * 2009-03-30 2013-10-09 国立大学法人神戸大学 共有キャッシュメモリとそのキャッシュ間のデータ転送方法
JP5397843B2 (ja) * 2009-08-18 2014-01-22 国立大学法人神戸大学 キャッシュメモリとそのモード切替方法
JP5267437B2 (ja) * 2009-11-20 2013-08-21 富士通セミコンダクター株式会社 半導体記憶装置、半導体装置、及び半導体記憶装置の制御方法
US8561078B2 (en) 2011-09-27 2013-10-15 Throughputer, Inc. Task switching and inter-task communications for multi-core processors
US20130117168A1 (en) 2011-11-04 2013-05-09 Mark Henrik Sandstrom Maximizing Throughput of Multi-user Parallel Data Processing Systems
US8789065B2 (en) 2012-06-08 2014-07-22 Throughputer, Inc. System and method for input data load adaptive parallel processing
US8490111B2 (en) * 2011-04-16 2013-07-16 Throughputer, Inc. Efficient network and memory architecture for multi-core data processing system
GB2490766B (en) * 2011-04-16 2013-04-24 Mark Henrik Sandstrom Task switching and inter-task communications for multi-core processors
US9448847B2 (en) 2011-07-15 2016-09-20 Throughputer, Inc. Concurrent program execution optimization
WO2014073374A1 (en) * 2012-11-06 2014-05-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
TWI764749B (zh) * 2021-06-07 2022-05-11 嘉雨思科技股份有限公司 訊號傳輸電路元件、多工器電路元件及解多工器電路元件

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4449199A (en) * 1980-11-12 1984-05-15 Diasonics Cardio/Imaging, Inc. Ultrasound scan conversion and memory system
US4434502A (en) * 1981-04-03 1984-02-28 Nippon Electric Co., Ltd. Memory system handling a plurality of bits as a unit to be processed
US4468727A (en) * 1981-05-14 1984-08-28 Honeywell Inc. Integrated cellular array parallel processor
US4713756A (en) * 1985-02-28 1987-12-15 Westinghouse Electric Corp. Non-volatile memory device for a programmable controller
US4942575A (en) * 1988-06-17 1990-07-17 Modular Computer Systems, Inc. Error connection device for parity protected memory systems

Also Published As

Publication number Publication date
ATE129593T1 (de) 1995-11-15
EP0375105A3 (de) 1992-03-18
EP0375105A2 (de) 1990-06-27
US5031146A (en) 1991-07-09
DE68924637T2 (de) 1996-06-13
EP0375105B1 (de) 1995-10-25
JPH02259866A (ja) 1990-10-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee