DE68924501D1 - Speichersubsystem mit Fehlerkorrekturcache-Speicher. - Google Patents

Speichersubsystem mit Fehlerkorrekturcache-Speicher.

Info

Publication number
DE68924501D1
DE68924501D1 DE68924501T DE68924501T DE68924501D1 DE 68924501 D1 DE68924501 D1 DE 68924501D1 DE 68924501 T DE68924501 T DE 68924501T DE 68924501 T DE68924501 T DE 68924501T DE 68924501 D1 DE68924501 D1 DE 68924501D1
Authority
DE
Germany
Prior art keywords
cache
storage
real
vector processor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924501T
Other languages
English (en)
Other versions
DE68924501T2 (de
Inventor
Patrick Francis Dutton
Steven Lee Gregor
Hehching Harry Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68924501D1 publication Critical patent/DE68924501D1/de
Publication of DE68924501T2 publication Critical patent/DE68924501T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
DE68924501T 1988-06-28 1989-04-18 Speichersubsystem mit Fehlerkorrekturcache-Speicher. Expired - Fee Related DE68924501T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21243288A 1988-06-28 1988-06-28

Publications (2)

Publication Number Publication Date
DE68924501D1 true DE68924501D1 (de) 1995-11-16
DE68924501T2 DE68924501T2 (de) 1996-06-13

Family

ID=22790982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924501T Expired - Fee Related DE68924501T2 (de) 1988-06-28 1989-04-18 Speichersubsystem mit Fehlerkorrekturcache-Speicher.

Country Status (4)

Country Link
EP (1) EP0348616B1 (de)
JP (1) JPH0245845A (de)
BR (1) BR8903173A (de)
DE (1) DE68924501T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5269009A (en) * 1990-09-04 1993-12-07 International Business Machines Corporation Processor system with improved memory transfer means
US5717895A (en) * 1994-12-01 1998-02-10 Cray Research, Inc. Associative scalar data cache with write-through capabilities for a vector processor
JP3153765B2 (ja) * 1996-06-24 2001-04-09 矢崎総業株式会社 平型回路体とコネクタの接続構造
GB2390700B (en) * 2002-04-15 2006-03-15 Alphamosaic Ltd Narrow/wide cache
US6922754B2 (en) 2002-12-09 2005-07-26 Infabric Technologies, Inc. Data-aware data flow manager
DE102012203640A1 (de) 2012-03-08 2013-09-12 Robert Bosch Gmbh Verfahren zum Lösen einer Rückhalteeinrichtung für einen Aufsaßen auf einem Fahrzeug und ein diesbezügliches Fahrzeug
US11296467B2 (en) 2012-11-06 2022-04-05 Server Technology, Inc. High outlet density power distribution unit
US9477550B2 (en) 2013-10-24 2016-10-25 Globalfoundries Inc. ECC bypass using low latency CE correction with retry select signal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
JPS61169949A (ja) * 1985-01-22 1986-07-31 Fujitsu Ltd バツフアメモリ制御方式
JPS6237754A (ja) * 1985-08-13 1987-02-18 Fujitsu Ltd 仮想拡張記憶方式

Also Published As

Publication number Publication date
EP0348616B1 (de) 1995-10-11
DE68924501T2 (de) 1996-06-13
JPH0245845A (ja) 1990-02-15
JPH0574101B2 (de) 1993-10-15
EP0348616A3 (de) 1991-03-13
BR8903173A (pt) 1990-03-06
EP0348616A2 (de) 1990-01-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee