DE68923487T2 - Elektronischer Speicher. - Google Patents

Elektronischer Speicher.

Info

Publication number
DE68923487T2
DE68923487T2 DE68923487T DE68923487T DE68923487T2 DE 68923487 T2 DE68923487 T2 DE 68923487T2 DE 68923487 T DE68923487 T DE 68923487T DE 68923487 T DE68923487 T DE 68923487T DE 68923487 T2 DE68923487 T2 DE 68923487T2
Authority
DE
Germany
Prior art keywords
sub
floating gate
wdl
tunnel
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923487T
Other languages
English (en)
Other versions
DE68923487D1 (de
Inventor
Nader Radjy
Michael Briner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vantis Corp
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE68923487D1 publication Critical patent/DE68923487D1/de
Publication of DE68923487T2 publication Critical patent/DE68923487T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Saccharide Compounds (AREA)
DE68923487T 1988-06-15 1989-06-07 Elektronischer Speicher. Expired - Fee Related DE68923487T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/207,323 US5005155A (en) 1988-06-15 1988-06-15 Optimized electrically erasable PLA cell for minimum read disturb

Publications (2)

Publication Number Publication Date
DE68923487D1 DE68923487D1 (de) 1995-08-24
DE68923487T2 true DE68923487T2 (de) 1996-03-21

Family

ID=22770053

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923487T Expired - Fee Related DE68923487T2 (de) 1988-06-15 1989-06-07 Elektronischer Speicher.

Country Status (5)

Country Link
US (1) US5005155A (de)
EP (2) EP0347093B1 (de)
JP (1) JP2688612B2 (de)
AT (1) ATE125385T1 (de)
DE (1) DE68923487T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170373A (en) * 1989-10-31 1992-12-08 Sgs-Thomson Microelectronics, Inc. Three transistor eeprom cell
EP0463378B1 (de) * 1990-06-29 1997-03-05 Texas Instruments Incorporated Elektrisch löschbare, elektrisch programmierbare Festwertspeicherzelle mit wählbarer Schwellspannung und Verfahren zu ihrer Verwendung
JP2829156B2 (ja) * 1991-07-25 1998-11-25 株式会社東芝 不揮発性半導体記憶装置の冗長回路
US5247478A (en) * 1992-03-06 1993-09-21 Altera Corporation Programmable transfer-devices
WO1995030226A1 (en) * 1994-04-29 1995-11-09 Atmel Corporation High-speed, non-volatile electrically programmable and erasable cell and method
TW318961B (de) * 1994-05-04 1997-11-01 Nippon Precision Circuits
WO1996001499A1 (en) * 1994-07-05 1996-01-18 Zycad Corporation A general purpose, non-volatile reprogrammable switch
US5648669A (en) * 1995-05-26 1997-07-15 Cypress Semiconductor High speed flash memory cell structure and method
US5742542A (en) * 1995-07-03 1998-04-21 Advanced Micro Devices, Inc. Non-volatile memory cells using only positive charge to store data
US5640344A (en) * 1995-07-25 1997-06-17 Btr, Inc. Programmable non-volatile bidirectional switch for programmable logic
US5581501A (en) * 1995-08-17 1996-12-03 Altera Corporation Nonvolatile SRAM cells and cell arrays
US6331724B1 (en) * 1995-11-17 2001-12-18 Nippon Precision Circuits, Inc. Single transistor E2prom memory device with controlled erasing
EP0778581B1 (de) * 1995-12-07 2002-08-14 Samsung Electronics Co., Ltd. Nichtflüchtige Speicheranordnung
US6005806A (en) 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
US5949710A (en) * 1996-04-10 1999-09-07 Altera Corporation Programmable interconnect junction
US5959891A (en) * 1996-08-16 1999-09-28 Altera Corporation Evaluation of memory cell characteristics
US6018476A (en) * 1996-09-16 2000-01-25 Altera Corporation Nonvolatile configuration cells and cell arrays
US6236597B1 (en) 1996-09-16 2001-05-22 Altera Corporation Nonvolatile memory cell with multiple gate oxide thicknesses
US5914904A (en) * 1996-10-01 1999-06-22 Altera Corporation Compact electrically erasable memory cells and arrays
US5986931A (en) * 1997-01-02 1999-11-16 Caywood; John M. Low voltage single CMOS electrically erasable read-only memory
US6201732B1 (en) 1997-01-02 2001-03-13 John M. Caywood Low voltage single CMOS electrically erasable read-only memory
US5905675A (en) * 1997-03-20 1999-05-18 Altera Corporation Biasing scheme for reducing stress and improving reliability in EEPROM cells
US6268623B1 (en) 1997-03-20 2001-07-31 Altera Corporation Apparatus and method for margin testing single polysilicon EEPROM cells
US6781883B1 (en) 1997-03-20 2004-08-24 Altera Corporation Apparatus and method for margin testing single polysilicon EEPROM cells
US5847993A (en) * 1997-06-23 1998-12-08 Xilinx, Inc. Non-volatile programmable CMOS logic cell and method of operating same
US5912836A (en) * 1997-12-01 1999-06-15 Amic Technology, Inc. Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array
JP4530464B2 (ja) * 2000-03-09 2010-08-25 ルネサスエレクトロニクス株式会社 半導体集積回路
CN100461424C (zh) * 2003-12-30 2009-02-11 中芯国际集成电路制造(上海)有限公司 半导体集成电路隧道氧化窗口区域设计的结构及方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034198B2 (ja) * 1980-11-26 1985-08-07 富士通株式会社 不揮発性メモリ
US4546454A (en) * 1982-11-05 1985-10-08 Seeq Technology, Inc. Non-volatile memory cell fuse element
US4654825A (en) * 1984-01-06 1987-03-31 Advanced Micro Devices, Inc. E2 prom memory cell
DE3468592D1 (en) * 1984-05-07 1988-02-11 Itt Ind Gmbh Deutsche Semiconductor memory cell having an electrically floating memory gate
US4628487A (en) * 1984-08-14 1986-12-09 Texas Instruments Incorporated Dual slope, feedback controlled, EEPROM programming
WO1986005323A1 (en) * 1985-03-08 1986-09-12 Ncr Corporation Floating gate nonvolatile field effect memory device
US4663740A (en) * 1985-07-01 1987-05-05 Silicon Macrosystems Incorporated High speed eprom cell and array
US4695979A (en) * 1985-09-09 1987-09-22 Texas Instruments Incorporated Modified four transistor EEPROM cell
US4715014A (en) * 1985-10-29 1987-12-22 Texas Instruments Incorporated Modified three transistor EEPROM cell
JP2554620B2 (ja) * 1985-12-12 1996-11-13 株式会社東芝 不揮発性半導体記憶装置
EP0265554A1 (de) * 1986-10-31 1988-05-04 INTERSIL, INC. (a Delaware corp.) Mit elektrisch löschbaren Sicherungen versehenes programmierbares logisches Feld
JPH0640589B2 (ja) * 1987-03-16 1994-05-25 株式会社東芝 不揮発性半導体記憶装置
US4788663A (en) * 1987-04-24 1988-11-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with a lightly-doped drain structure

Also Published As

Publication number Publication date
EP0582319A2 (de) 1994-02-09
EP0347093B1 (de) 1995-07-19
US5005155A (en) 1991-04-02
EP0347093A2 (de) 1989-12-20
EP0582319A3 (de) 1994-03-23
ATE125385T1 (de) 1995-08-15
JPH02103796A (ja) 1990-04-16
EP0347093A3 (de) 1992-03-11
DE68923487D1 (de) 1995-08-24
JP2688612B2 (ja) 1997-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL

8339 Ceased/non-payment of the annual fee