DE3468592D1 - Semiconductor memory cell having an electrically floating memory gate - Google Patents

Semiconductor memory cell having an electrically floating memory gate

Info

Publication number
DE3468592D1
DE3468592D1 DE8484105116T DE3468592T DE3468592D1 DE 3468592 D1 DE3468592 D1 DE 3468592D1 DE 8484105116 T DE8484105116 T DE 8484105116T DE 3468592 T DE3468592 T DE 3468592T DE 3468592 D1 DE3468592 D1 DE 3468592D1
Authority
DE
Germany
Prior art keywords
electrically floating
gate
memory cell
tsn
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484105116T
Other languages
German (de)
Inventor
Fritz Gunther Dr Rer Nat Adam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Application granted granted Critical
Publication of DE3468592D1 publication Critical patent/DE3468592D1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The cell employs a source/drain series circuit containing several storage transistors (Ts1...Tsn), each of which exhibits a floating gate (Fg1...Fgn), with an associated injector (I1...In). Enhancement type storage transistors (Ts1...Tsn) are used, their programme gates coupled in common to the programme line (P). The injectors (I1...In) are pref. controlled via the source/ drain path of an injector selection transistor (Tai) with its gate coupled to the word line (Z).
DE8484105116T 1984-05-07 1984-05-07 Semiconductor memory cell having an electrically floating memory gate Expired DE3468592D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84105116A EP0160720B1 (en) 1984-05-07 1984-05-07 Semiconductor memory cell having an electrically floating memory gate

Publications (1)

Publication Number Publication Date
DE3468592D1 true DE3468592D1 (en) 1988-02-11

Family

ID=8191928

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484105116T Expired DE3468592D1 (en) 1984-05-07 1984-05-07 Semiconductor memory cell having an electrically floating memory gate

Country Status (5)

Country Link
US (1) US4580247A (en)
EP (1) EP0160720B1 (en)
JP (1) JPS60246099A (en)
AU (1) AU4171085A (en)
DE (1) DE3468592D1 (en)

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US4787047A (en) * 1985-03-22 1988-11-22 Intersil Electrically erasable fused programmable logic array
US4933904A (en) * 1985-11-29 1990-06-12 General Electric Company Dense EPROM having serially coupled floating gate transistors
US4758988A (en) * 1985-12-12 1988-07-19 Motorola, Inc. Dual array EEPROM for high endurance capability
US5719805A (en) * 1987-04-24 1998-02-17 Kabushiki Kaisha Toshiba Electrically programmable non-volatile semiconductor memory including series connected memory cells and decoder circuitry for applying a ground voltage to non-selected circuit units
US5245566A (en) * 1987-04-24 1993-09-14 Fujio Masuoka Programmable semiconductor
US5313420A (en) * 1987-04-24 1994-05-17 Kabushiki Kaisha Toshiba Programmable semiconductor memory
US5448517A (en) * 1987-06-29 1995-09-05 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
US6545913B2 (en) 1987-06-29 2003-04-08 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US6034899A (en) * 1987-06-29 2000-03-07 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US5270969A (en) * 1987-06-29 1993-12-14 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with nand cell structure
US5877981A (en) * 1987-06-29 1999-03-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a matrix of memory cells
US5008856A (en) * 1987-06-29 1991-04-16 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
JP2856395B2 (en) * 1987-11-09 1999-02-10 日本電気アイシーマイコンシステム株式会社 Semiconductor integrated circuit
US4939690A (en) * 1987-12-28 1990-07-03 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation
US4845538A (en) * 1988-02-05 1989-07-04 Emanuel Hazani E2 prom cell including isolated control diffusion
US4855955A (en) * 1988-04-08 1989-08-08 Seeq Technology, Inc. Three transistor high endurance eeprom cell
JPH01273350A (en) * 1988-04-25 1989-11-01 Nec Corp Nonvolatile semiconductor storage device
US5005155A (en) * 1988-06-15 1991-04-02 Advanced Micro Devices, Inc. Optimized electrically erasable PLA cell for minimum read disturb
US5295096A (en) * 1988-07-11 1994-03-15 Mitsubishi Denki Kabushiki Kaisha NAND type EEPROM and operating method therefor
KR910007434B1 (en) * 1988-12-15 1991-09-26 삼성전자 주식회사 Eeprom and the programming method
JP2580752B2 (en) * 1988-12-27 1997-02-12 日本電気株式会社 Nonvolatile semiconductor memory device
KR910004166B1 (en) * 1988-12-27 1991-06-22 삼성전자주식회사 Eeprom having nand-cells
JP3060680B2 (en) * 1990-11-30 2000-07-10 日本電気株式会社 Nonvolatile semiconductor memory device
JP3342730B2 (en) * 1993-03-17 2002-11-11 富士通株式会社 Nonvolatile semiconductor memory device
EP0655743B1 (en) * 1993-11-30 1999-08-25 STMicroelectronics S.r.l. Integrated circuit for the programming of a memory cell in a non-volatile memory register
JP3450467B2 (en) * 1993-12-27 2003-09-22 株式会社東芝 Nonvolatile semiconductor memory device and method of manufacturing the same
US5889410A (en) * 1996-05-22 1999-03-30 International Business Machines Corporation Floating gate interlevel defect monitor and method
US7450433B2 (en) * 2004-12-29 2008-11-11 Sandisk Corporation Word line compensation in non-volatile memory erase operations
US7403424B2 (en) * 2005-03-31 2008-07-22 Sandisk Corporation Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US7522457B2 (en) * 2005-03-31 2009-04-21 Sandisk Corporation Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
US7457166B2 (en) * 2005-03-31 2008-11-25 Sandisk Corporation Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
US7499317B2 (en) * 2006-10-13 2009-03-03 Sandisk Corporation System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling
US7499338B2 (en) * 2006-10-13 2009-03-03 Sandisk Corporation Partitioned soft programming in non-volatile memory
US7535766B2 (en) * 2006-10-13 2009-05-19 Sandisk Corporation Systems for partitioned soft programming in non-volatile memory
US7495954B2 (en) * 2006-10-13 2009-02-24 Sandisk Corporation Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory
JP5467761B2 (en) * 2008-12-01 2014-04-09 ローム株式会社 EEPROM
JP5301020B2 (en) * 2012-07-24 2013-09-25 ルネサスエレクトロニクス株式会社 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0053075B1 (en) * 1980-11-26 1988-04-20 Fujitsu Limited Nonvolatile memory
JPS57130298A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor integrated circuit memory and relieving method for its fault

Also Published As

Publication number Publication date
JPH0451917B2 (en) 1992-08-20
US4580247A (en) 1986-04-01
EP0160720B1 (en) 1988-01-07
JPS60246099A (en) 1985-12-05
AU4171085A (en) 1985-11-14
EP0160720A1 (en) 1985-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MICRONAS INTERMETALL GMBH, 79108 FREIBURG, DE

8327 Change in the person/name/address of the patent owner

Owner name: MICRONAS GMBH, 79108 FREIBURG, DE

8339 Ceased/non-payment of the annual fee