DE68916612D1 - ECL/CMOS-Pegelwandler. - Google Patents

ECL/CMOS-Pegelwandler.

Info

Publication number
DE68916612D1
DE68916612D1 DE68916612T DE68916612T DE68916612D1 DE 68916612 D1 DE68916612 D1 DE 68916612D1 DE 68916612 T DE68916612 T DE 68916612T DE 68916612 T DE68916612 T DE 68916612T DE 68916612 D1 DE68916612 D1 DE 68916612D1
Authority
DE
Germany
Prior art keywords
ecl
level converter
cmos level
cmos
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916612T
Other languages
English (en)
Other versions
DE68916612T2 (de
Inventor
Ikuo Jimmy Sanwo
John David Simeral
Richard Allyn Daniel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE68916612D1 publication Critical patent/DE68916612D1/de
Publication of DE68916612T2 publication Critical patent/DE68916612T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE68916612T 1988-10-19 1989-10-19 ECL/CMOS-Pegelwandler. Expired - Fee Related DE68916612T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/259,838 US4888501A (en) 1988-10-19 1988-10-19 ECL to CMOS converter

Publications (2)

Publication Number Publication Date
DE68916612D1 true DE68916612D1 (de) 1994-08-11
DE68916612T2 DE68916612T2 (de) 1995-03-23

Family

ID=22986624

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916612T Expired - Fee Related DE68916612T2 (de) 1988-10-19 1989-10-19 ECL/CMOS-Pegelwandler.

Country Status (5)

Country Link
US (1) US4888501A (de)
EP (1) EP0365331B1 (de)
JP (1) JPH02125523A (de)
CA (1) CA1304459C (de)
DE (1) DE68916612T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738580B2 (ja) * 1988-09-30 1995-04-26 日本電気株式会社 エミッタ結合論理回路
US5059829A (en) * 1990-09-04 1991-10-22 Motorola, Inc. Logic level shifting circuit with minimal delay
US5371424A (en) * 1992-11-25 1994-12-06 Motorola, Inc. Transmitter/receiver circuit and method therefor
JP3623004B2 (ja) * 1994-03-30 2005-02-23 松下電器産業株式会社 電圧レベル変換回路
US5534812A (en) * 1995-04-21 1996-07-09 International Business Machines Corporation Communication between chips having different voltage levels
US6008682A (en) * 1996-06-14 1999-12-28 Sun Microsystems, Inc. Circuit and method for selectively enabling ECL type outputs
US6211699B1 (en) 1999-04-14 2001-04-03 Micro Linear Corporation High performance CML to CMOS converter
JP3635466B2 (ja) * 2002-09-30 2005-04-06 日本テキサス・インスツルメンツ株式会社 レベルシフト回路
JP6954845B2 (ja) * 2018-01-09 2021-10-27 株式会社東海理化電機製作所 レベルシフト装置、及びｉｃ装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3946246A (en) * 1974-09-03 1976-03-23 Motorola, Inc. Fully compensated emitter coupled logic gate
US4128775A (en) * 1977-06-22 1978-12-05 National Semiconductor Corporation Voltage translator for interfacing TTL and CMOS circuits
JPS58125915A (ja) * 1981-12-29 1983-07-27 Fujitsu Ltd バイアス回路
US4437171A (en) * 1982-01-07 1984-03-13 Intel Corporation ECL Compatible CMOS memory
US4453095A (en) * 1982-07-16 1984-06-05 Motorola Inc. ECL MOS Buffer circuits
US4496856A (en) * 1982-07-21 1985-01-29 Sperry Corporation GaAs to ECL level converter
JPS5943631A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd レベル変換入力回路
US4645951A (en) * 1983-08-31 1987-02-24 Hitachi, Ltd. Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals
JPS6119226A (ja) * 1984-07-05 1986-01-28 Hitachi Ltd レベル変換回路
US4680480A (en) * 1984-08-31 1987-07-14 Storage Technology Corporation Output driver circuit for LSI and VLSI ECL chips with an active pulldown
US4742247A (en) * 1985-04-26 1988-05-03 Advanced Micro Devices, Inc. CMOS address transition detector with temperature compensation
US4656375A (en) * 1985-12-16 1987-04-07 Ncr Corporation Temperature compensated CMOS to ECL translator
US4785205A (en) * 1987-06-29 1988-11-15 Ncr Corporation High speed ECL to CMOS converter

Also Published As

Publication number Publication date
US4888501A (en) 1989-12-19
CA1304459C (en) 1992-06-30
DE68916612T2 (de) 1995-03-23
EP0365331B1 (de) 1994-07-06
JPH02125523A (ja) 1990-05-14
EP0365331A1 (de) 1990-04-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8339 Ceased/non-payment of the annual fee