DE68911761D1 - Parallel/Serienumsetzer. - Google Patents

Parallel/Serienumsetzer.

Info

Publication number
DE68911761D1
DE68911761D1 DE89110879T DE68911761T DE68911761D1 DE 68911761 D1 DE68911761 D1 DE 68911761D1 DE 89110879 T DE89110879 T DE 89110879T DE 68911761 T DE68911761 T DE 68911761T DE 68911761 D1 DE68911761 D1 DE 68911761D1
Authority
DE
Germany
Prior art keywords
parallel
serial converter
converter
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89110879T
Other languages
English (en)
Other versions
DE68911761T2 (de
Inventor
Kazuo Yamane
Masanori Shimasue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE68911761D1 publication Critical patent/DE68911761D1/de
Application granted granted Critical
Publication of DE68911761T2 publication Critical patent/DE68911761T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
DE68911761T 1988-06-16 1989-06-15 Parallel/Serienumsetzer. Expired - Fee Related DE68911761T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63148662A JPH0773219B2 (ja) 1988-06-16 1988-06-16 並直列変換装置

Publications (2)

Publication Number Publication Date
DE68911761D1 true DE68911761D1 (de) 1994-02-10
DE68911761T2 DE68911761T2 (de) 1994-06-09

Family

ID=15457817

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68911761T Expired - Fee Related DE68911761T2 (de) 1988-06-16 1989-06-15 Parallel/Serienumsetzer.

Country Status (5)

Country Link
US (1) US4965797A (de)
EP (1) EP0346896B1 (de)
JP (1) JPH0773219B2 (de)
CA (1) CA1304845C (de)
DE (1) DE68911761T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
FR2664765B1 (fr) * 1990-07-11 2003-05-16 Bull Sa Dispositif de serialisation et de deserialisation de donnees et systeme de transmission numerique de donnees en serie en resultant.
US5111455A (en) * 1990-08-24 1992-05-05 Avantek, Inc. Interleaved time-division multiplexor with phase-compensated frequency doublers
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
JPH04141896A (ja) * 1990-10-02 1992-05-15 Nec Corp シリアル・パラレル変換回路
US5282210A (en) * 1992-06-01 1994-01-25 International Business Machines Corporation Time-division-multiplexed data transmission system
SE515076C2 (sv) * 1992-07-01 2001-06-05 Ericsson Telefon Ab L M Multiplexor-/demultiplexorkrets
JPH06152556A (ja) * 1992-10-30 1994-05-31 Ando Electric Co Ltd データ多重回路
US5406607A (en) * 1994-02-24 1995-04-11 Convex Computer Corporation Apparatus, systems and methods for addressing electronic memories
JP3166494B2 (ja) * 1994-07-27 2001-05-14 松下電器産業株式会社 遅延検波方法および装置
US5768283A (en) * 1994-11-08 1998-06-16 Washington University Digital phase adjustment circuit for asynchronous transfer mode and like data formats
FR2727587A1 (fr) * 1994-11-30 1996-05-31 Sgs Thomson Microelectronics Dispositif de serialisation de donnees binaires a haut debit
US5724361A (en) * 1996-03-12 1998-03-03 Lsi Logic Corporation High performance n:1 multiplexer with overlap control of multi-phase clocks
US5867543A (en) * 1996-03-29 1999-02-02 Dsc Communications Corporation Multi-rate transmission system
SE506817C2 (sv) * 1996-06-20 1998-02-16 Ericsson Telefon Ab L M Seriell-parallell- och parallell-seriellomvandlare innefattande frekvensdelare
US5805089A (en) * 1996-09-05 1998-09-08 Lsi Logic Corporation Time-division data multiplexer with feedback for clock cross-over adjustment
DE19652003C1 (de) * 1996-12-13 1997-10-09 Siemens Ag Parallel/Seriell-Wandler
US6202108B1 (en) * 1997-03-13 2001-03-13 Bull S.A. Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies
DE19716314A1 (de) 1997-04-18 1998-10-22 Alsthom Cge Alcatel Verfahren und Vorrichtung zur Addition von als Abtastwerte vorliegenden Signalen
EP0974888A1 (de) * 1998-07-18 2000-01-26 PIRELLI CAVI E SISTEMI S.p.A. Optische Einheit für die Verarbeitung einer vorbestimmten optischen Reihenfolge von N-Bits
US6879650B1 (en) * 1998-09-23 2005-04-12 Paradyne Corporation Circuit and method for detecting and correcting data clocking errors
JP2000278141A (ja) * 1999-03-26 2000-10-06 Mitsubishi Electric Corp マルチプレクサ
US6298400B1 (en) * 1999-10-13 2001-10-02 Sony Corporation Enhancing interface device to transport stream of parallel signals to serial signals with separate clock rate using a pin reassignment
US6977980B2 (en) * 2001-08-29 2005-12-20 Rambus Inc. Timing synchronization methods and systems for transmit parallel interfaces
US7576734B2 (en) * 2001-10-30 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Signal line driving circuit, light emitting device, and method for driving the same
JP4242741B2 (ja) * 2003-09-19 2009-03-25 パナソニック株式会社 デバッグ用信号処理回路
KR100719343B1 (ko) * 2005-02-28 2007-05-17 삼성전자주식회사 독립적인 클럭 소스를 기준으로 직렬 클럭을 생성하는 직렬변환기와 데이터의 직렬 전송 방법
US8405426B2 (en) * 2010-05-28 2013-03-26 Qualcomm Incorporated Method and apparatus to serialize parallel data input values
JP2013125561A (ja) * 2011-12-14 2013-06-24 Elpida Memory Inc 半導体装置
US20150229327A1 (en) * 2014-02-12 2015-08-13 Fujitsu Limited Multiplexer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542504A (en) * 1983-08-22 1985-09-17 At&T Bell Laboratories Shared data receiver
US4575860A (en) * 1984-03-12 1986-03-11 At&T Bell Laboratories Data clock recovery circuit
NL8501737A (nl) * 1985-06-17 1987-01-16 At & T & Philips Telecomm Hogere orde digitaal transmissiesysteem voorzien van een multiplexer en een demultiplexer.
GB2180725B (en) * 1985-09-19 1989-01-25 Stc Plc Digital communication circuit
JPS6330034A (ja) * 1986-07-23 1988-02-08 Nec Corp 多重化回路
US4791488A (en) * 1987-08-12 1988-12-13 Rca Licensing Corporation Line-locked clock signal generation system

Also Published As

Publication number Publication date
EP0346896B1 (de) 1993-12-29
JPH01317026A (ja) 1989-12-21
DE68911761T2 (de) 1994-06-09
US4965797A (en) 1990-10-23
EP0346896A2 (de) 1989-12-20
JPH0773219B2 (ja) 1995-08-02
CA1304845C (en) 1992-07-07
EP0346896A3 (en) 1990-11-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee