DE68905425D1 - Halbleiteranordnung mit einer steuerelektrode, bestehend aus einer mehrzahl von schichten. - Google Patents
Halbleiteranordnung mit einer steuerelektrode, bestehend aus einer mehrzahl von schichten.Info
- Publication number
- DE68905425D1 DE68905425D1 DE8989117743T DE68905425T DE68905425D1 DE 68905425 D1 DE68905425 D1 DE 68905425D1 DE 8989117743 T DE8989117743 T DE 8989117743T DE 68905425 T DE68905425 T DE 68905425T DE 68905425 D1 DE68905425 D1 DE 68905425D1
- Authority
- DE
- Germany
- Prior art keywords
- control electrode
- multiple layer
- semiconductor arrangement
- semiconductor
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63240002A JP2755613B2 (ja) | 1988-09-26 | 1988-09-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68905425D1 true DE68905425D1 (de) | 1993-04-22 |
DE68905425T2 DE68905425T2 (de) | 1993-09-09 |
Family
ID=17053003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8989117743T Expired - Fee Related DE68905425T2 (de) | 1988-09-26 | 1989-09-26 | Halbleiteranordnung mit einer steuerelektrode, bestehend aus einer mehrzahl von schichten. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5053840A (de) |
EP (1) | EP0364769B1 (de) |
JP (1) | JP2755613B2 (de) |
KR (1) | KR930003560B1 (de) |
DE (1) | DE68905425T2 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5304829A (en) * | 1989-01-17 | 1994-04-19 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor device |
US5087584A (en) * | 1990-04-30 | 1992-02-11 | Intel Corporation | Process for fabricating a contactless floating gate memory array utilizing wordline trench vias |
IT1243303B (it) * | 1990-07-24 | 1994-05-26 | Sgs Thomson Microelectronics | Schieramento di celle di memoria con linee metalliche di connessione di source e di drain formate sul substrato ed ortogonalmente sovrastate da linee di connessione di gate e procedimento per la sua fabbricazione |
JP2893894B2 (ja) * | 1990-08-15 | 1999-05-24 | 日本電気株式会社 | 不揮発性メモリ及びその製造方法 |
JP2793722B2 (ja) * | 1991-01-29 | 1998-09-03 | 富士通株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
US5877054A (en) * | 1995-06-29 | 1999-03-02 | Sharp Kabushiki Kaisha | Method of making nonvolatile semiconductor memory |
EP0752721B1 (de) * | 1995-06-29 | 2009-04-29 | Sharp Kabushiki Kaisha | Nichtflüchtiger Halbleiterspeicher und Verfahren zur Steuerung und Verfahren zu seiner Herstellung |
JP3366173B2 (ja) * | 1995-07-31 | 2003-01-14 | シャープ株式会社 | 不揮発性半導体メモリの製造方法 |
US5789298A (en) * | 1996-11-04 | 1998-08-04 | Advanced Micro Devices, Inc. | High performance mosfet structure having asymmetrical spacer formation and method of making the same |
US6091100A (en) * | 1998-02-06 | 2000-07-18 | Texas Instruments - Acer Incorporated | High density NAND structure nonvolatile memories |
JP3264241B2 (ja) | 1998-02-10 | 2002-03-11 | 日本電気株式会社 | 半導体装置の製造方法 |
DE19808182C1 (de) * | 1998-02-26 | 1999-08-12 | Siemens Ag | Elektrisch programmierbare Speicherzellenanordnung und ein Verfahren zu deren Herstellung |
US6020606A (en) * | 1998-03-20 | 2000-02-01 | United Silicon Incorporated | Structure of a memory cell |
KR100295136B1 (ko) * | 1998-04-13 | 2001-09-17 | 윤종용 | 불휘발성메모리장치및그제조방법 |
JP3097657B2 (ja) * | 1998-05-13 | 2000-10-10 | 日本電気株式会社 | 半導体記憶装置とその製造方法 |
US6117762A (en) | 1999-04-23 | 2000-09-12 | Hrl Laboratories, Llc | Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering |
US6396368B1 (en) | 1999-11-10 | 2002-05-28 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
US6815816B1 (en) | 2000-10-25 | 2004-11-09 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
DE10058947A1 (de) * | 2000-11-28 | 2002-07-18 | Infineon Technologies Ag | Nichtflüchtige NOR-Eintransistor-Halbleiterspeicherzelle sowie dazugehörige Halbleiterspeichereinrichtung, Herstellungsverfahren und Verfahren zu deren Programmierung |
DE10062245A1 (de) * | 2000-12-14 | 2002-07-04 | Infineon Technologies Ag | Nichtflüchtige Halbleiterspeicherzelle sowie dazugehörige Halbleiterschaltungsanordnung und Verfahren zu deren Herstellung |
US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
DE10110150A1 (de) | 2001-03-02 | 2002-09-19 | Infineon Technologies Ag | Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray |
US6774413B2 (en) | 2001-06-15 | 2004-08-10 | Hrl Laboratories, Llc | Integrated circuit structure with programmable connector/isolator |
US6740942B2 (en) | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
KR100485486B1 (ko) * | 2002-09-19 | 2005-04-27 | 동부아남반도체 주식회사 | 플래시 메모리 셀의 구조 및 그 제조 방법 |
US7049667B2 (en) | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
WO2004055868A2 (en) | 2002-12-13 | 2004-07-01 | Hrl Laboratories, Llc | Integrated circuit modification using well implants |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
US8168487B2 (en) | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
US8754483B2 (en) | 2011-06-27 | 2014-06-17 | International Business Machines Corporation | Low-profile local interconnect and method of making the same |
US9064970B2 (en) | 2013-03-15 | 2015-06-23 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US9276011B2 (en) | 2013-03-15 | 2016-03-01 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
US9437604B2 (en) | 2013-11-01 | 2016-09-06 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
US9608000B2 (en) * | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4151021A (en) * | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
US4377818A (en) * | 1978-11-02 | 1983-03-22 | Texas Instruments Incorporated | High density electrically programmable ROM |
US4267632A (en) * | 1979-10-19 | 1981-05-19 | Intel Corporation | Process for fabricating a high density electrically programmable memory array |
JPS59126674A (ja) * | 1983-01-10 | 1984-07-21 | Toshiba Corp | 情報記憶用半導体装置 |
JPS60147165A (ja) * | 1984-01-12 | 1985-08-03 | Nec Corp | 不揮発性半導体メモリセル及びその使用方法 |
JPS60182174A (ja) * | 1984-02-28 | 1985-09-17 | Nec Corp | 不揮発性半導体メモリ |
US4763177A (en) * | 1985-02-19 | 1988-08-09 | Texas Instruments Incorporated | Read only memory with improved channel length isolation and method of forming |
US4597060A (en) * | 1985-05-01 | 1986-06-24 | Texas Instruments Incorporated | EPROM array and method for fabricating |
-
1988
- 1988-09-26 JP JP63240002A patent/JP2755613B2/ja not_active Expired - Fee Related
-
1989
- 1989-09-20 US US07/409,687 patent/US5053840A/en not_active Expired - Lifetime
- 1989-09-26 EP EP89117743A patent/EP0364769B1/de not_active Expired - Lifetime
- 1989-09-26 DE DE8989117743T patent/DE68905425T2/de not_active Expired - Fee Related
- 1989-09-26 KR KR1019890013817A patent/KR930003560B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0364769A3 (en) | 1990-05-02 |
US5053840A (en) | 1991-10-01 |
DE68905425T2 (de) | 1993-09-09 |
EP0364769A2 (de) | 1990-04-25 |
KR900005470A (ko) | 1990-04-14 |
JPH0287578A (ja) | 1990-03-28 |
JP2755613B2 (ja) | 1998-05-20 |
KR930003560B1 (ko) | 1993-05-06 |
EP0364769B1 (de) | 1993-03-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |