DE3888663D1 - Bipolare Halbleiteranordnung mit einer leitenden Rekombinationsschicht. - Google Patents

Bipolare Halbleiteranordnung mit einer leitenden Rekombinationsschicht.

Info

Publication number
DE3888663D1
DE3888663D1 DE88116087T DE3888663T DE3888663D1 DE 3888663 D1 DE3888663 D1 DE 3888663D1 DE 88116087 T DE88116087 T DE 88116087T DE 3888663 T DE3888663 T DE 3888663T DE 3888663 D1 DE3888663 D1 DE 3888663D1
Authority
DE
Germany
Prior art keywords
semiconductor device
bipolar semiconductor
recombination layer
conductive recombination
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88116087T
Other languages
English (en)
Other versions
DE3888663T2 (de
Inventor
Israel Arnold Lesk
Lowell Eugene Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE3888663D1 publication Critical patent/DE3888663D1/de
Application granted granted Critical
Publication of DE3888663T2 publication Critical patent/DE3888663T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE3888663T 1987-12-28 1988-09-29 Bipolare Halbleiteranordnung mit einer leitenden Rekombinationsschicht. Expired - Fee Related DE3888663T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/138,262 US4837177A (en) 1987-12-28 1987-12-28 Method of making bipolar semiconductor device having a conductive recombination layer

Publications (2)

Publication Number Publication Date
DE3888663D1 true DE3888663D1 (de) 1994-04-28
DE3888663T2 DE3888663T2 (de) 1994-08-04

Family

ID=22481227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3888663T Expired - Fee Related DE3888663T2 (de) 1987-12-28 1988-09-29 Bipolare Halbleiteranordnung mit einer leitenden Rekombinationsschicht.

Country Status (4)

Country Link
US (1) US4837177A (de)
EP (1) EP0323549B1 (de)
JP (1) JPH023266A (de)
DE (1) DE3888663T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9000972A (nl) * 1990-04-24 1991-11-18 Philips Nv Werkwijze voor het vervaardigen van een silicium lichaam met een n-type toplaag en een daaraan grenzende, hoger gedoteerde n-type basislaag.
US5141889A (en) * 1990-11-30 1992-08-25 Motorola, Inc. Method of making enhanced insulated gate bipolar transistor
US5693574A (en) * 1991-02-22 1997-12-02 Deutsche Aerospace Ag Process for the laminar joining of silicon semiconductor slices
US5256896A (en) * 1991-08-30 1993-10-26 International Business Machines Corporation Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor
US5496764A (en) * 1994-07-05 1996-03-05 Motorola, Inc. Process for forming a semiconductor region adjacent to an insulating layer
US5670387A (en) * 1995-01-03 1997-09-23 Motorola, Inc. Process for forming semiconductor-on-insulator device
JP2757815B2 (ja) * 1995-03-31 1998-05-25 日本電気株式会社 半導体装置の製造方法
DE19726126A1 (de) * 1997-06-20 1998-12-24 Telefunken Microelectron Bipolarer Schalttransistor mit verringerter Sättigung
DE19743265A1 (de) * 1997-09-30 1999-04-08 Siemens Ag Halbleiter-Leistungsbauelement mit erhöhter Latch-up-Festigkeit
DE19958694A1 (de) 1999-12-06 2001-06-13 Infineon Technologies Ag Steuerbares Halbleiterschaltelement
KR100444589B1 (ko) * 2002-07-27 2004-08-16 강재원 프로파일을 이용한 휴대용 낚시 좌대
WO2005021620A1 (ja) * 2003-08-29 2005-03-10 Toyo Boseki Kabushiki Kaisya ポリエステルフィルム
JP2006086457A (ja) * 2004-09-17 2006-03-30 Matsushita Electric Works Ltd 磁気検出装置
DE102005009725A1 (de) * 2005-03-03 2006-09-07 Atmel Germany Gmbh Verfahren zur Integration von zwei Bipolartransistoren in einen Halbleiterkörper, Halbleiteranordnung in einem Halbleiterkörper und Kaskodenschaltung

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1467354A (en) * 1974-05-10 1977-03-16 Gen Electric Power transistor
JPS5378788A (en) * 1976-12-23 1978-07-12 Hitachi Ltd Temperature-compensation-type constant voltage element
US4259683A (en) * 1977-02-07 1981-03-31 General Electric Company High switching speed P-N junction devices with recombination means centrally located in high resistivity layer
US4247862B1 (en) * 1977-08-26 1995-12-26 Intel Corp Ionzation resistant mos structure
US4200484A (en) * 1977-09-06 1980-04-29 Rockwell International Corporation Method of fabricating multiple layer composite
JPH061752B2 (ja) * 1983-12-06 1994-01-05 株式会社東芝 半導体ウエハの接合方法
JPS60191071A (ja) * 1984-03-09 1985-09-28 住友金属鉱山株式会社 耐凍害性に優れたａｌｃの製造方法
DE3583183D1 (de) * 1984-05-09 1991-07-18 Toshiba Kawasaki Kk Verfahren zur herstellung eines halbleitersubstrates.
JPS61145839A (ja) * 1984-12-20 1986-07-03 Toshiba Corp 半導体ウエ−ハの接着方法および接着治具
JPH0770476B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体装置の製造方法
JPH0624245B2 (ja) * 1985-02-08 1994-03-30 株式会社東芝 半導体装置の製造方法
US4752818A (en) * 1985-09-28 1988-06-21 Kabushiki Kaisha Toyota Chuo Kenkyusho Semiconductor device with multiple recombination center layers
JP2559700B2 (ja) * 1986-03-18 1996-12-04 富士通株式会社 半導体装置の製造方法
US4704785A (en) * 1986-08-01 1987-11-10 Texas Instruments Incorporated Process for making a buried conductor by fusing two wafers
US4701424A (en) * 1986-10-30 1987-10-20 Ford Motor Company Hermetic sealing of silicon
JPH0821678B2 (ja) * 1987-05-29 1996-03-04 日産自動車株式会社 半導体装置
US4774196A (en) * 1987-08-25 1988-09-27 Siliconix Incorporated Method of bonding semiconductor wafers

Also Published As

Publication number Publication date
US4837177A (en) 1989-06-06
EP0323549A2 (de) 1989-07-12
EP0323549A3 (en) 1989-12-06
JPH023266A (ja) 1990-01-08
EP0323549B1 (de) 1994-03-23
DE3888663T2 (de) 1994-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C. (N.D.GE

8339 Ceased/non-payment of the annual fee