DE60317963D1 - Verfahren zur Herstellung eines Halbleiterbauelements - Google Patents
Verfahren zur Herstellung eines HalbleiterbauelementsInfo
- Publication number
- DE60317963D1 DE60317963D1 DE60317963T DE60317963T DE60317963D1 DE 60317963 D1 DE60317963 D1 DE 60317963D1 DE 60317963 T DE60317963 T DE 60317963T DE 60317963 T DE60317963 T DE 60317963T DE 60317963 D1 DE60317963 D1 DE 60317963D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- semiconductor
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US112014 | 1980-01-14 | ||
US10/112,014 US6627510B1 (en) | 2002-03-29 | 2002-03-29 | Method of making self-aligned shallow trench isolation |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60317963D1 true DE60317963D1 (de) | 2008-01-24 |
DE60317963T2 DE60317963T2 (de) | 2008-11-27 |
Family
ID=28453218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60317963T Expired - Lifetime DE60317963T2 (de) | 2002-03-29 | 2003-03-10 | Verfahren zur Herstellung eines Halbleiterbauelements |
Country Status (6)
Country | Link |
---|---|
US (1) | US6627510B1 (de) |
EP (1) | EP1353369B1 (de) |
KR (1) | KR100515181B1 (de) |
CN (1) | CN1278407C (de) |
DE (1) | DE60317963T2 (de) |
TW (1) | TWI235450B (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5037766B2 (ja) * | 2001-09-10 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE10301291B3 (de) * | 2003-01-15 | 2004-08-26 | Infineon Technologies Ag | Verfahren zum Einbringen von eine unterschiedliche Dimensionierung aufweisenden Strukturen in ein Substrat |
US6716691B1 (en) * | 2003-06-25 | 2004-04-06 | Sharp Laboratories Of America, Inc. | Self-aligned shallow trench isolation process having improved polysilicon gate thickness control |
KR100514173B1 (ko) * | 2004-01-15 | 2005-09-09 | 삼성전자주식회사 | 반도체 장치의 게이트 형성 방법. |
US7012021B2 (en) * | 2004-01-29 | 2006-03-14 | Taiwan Semiconductor Mfg | Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device |
US8039339B2 (en) * | 2007-04-23 | 2011-10-18 | Freescale Semiconductor, Inc. | Separate layer formation in a semiconductor device |
CN102468212B (zh) * | 2010-11-15 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽隔离结构形成方法 |
CN102339746B (zh) * | 2011-09-28 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | 形成平坦介质层的方法 |
US9330959B2 (en) * | 2014-04-13 | 2016-05-03 | Texas Instruments Incorporated | Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation |
US10811320B2 (en) * | 2017-09-29 | 2020-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Footing removal in cut-metal process |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5238859A (en) * | 1988-04-26 | 1993-08-24 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JPH0370180A (ja) * | 1989-08-09 | 1991-03-26 | Fujitsu Ltd | 半導体装置の製造方法 |
US5202277A (en) * | 1989-12-08 | 1993-04-13 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device |
JP3174786B2 (ja) * | 1991-05-31 | 2001-06-11 | 富士通株式会社 | 半導体装置の製造方法 |
JP3057882B2 (ja) * | 1992-03-09 | 2000-07-04 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3202460B2 (ja) * | 1993-12-21 | 2001-08-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6069081A (en) * | 1995-04-28 | 2000-05-30 | International Buiness Machines Corporation | Two-step chemical mechanical polish surface planarization technique |
JP2790084B2 (ja) * | 1995-08-16 | 1998-08-27 | 日本電気株式会社 | 半導体装置の製造方法 |
DE19538005A1 (de) * | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
US5665202A (en) * | 1995-11-24 | 1997-09-09 | Motorola, Inc. | Multi-step planarization process using polishing at two different pad pressures |
US6091129A (en) * | 1996-06-19 | 2000-07-18 | Cypress Semiconductor Corporation | Self-aligned trench isolated structure |
JPH10125637A (ja) * | 1996-10-15 | 1998-05-15 | Toshiba Corp | 半導体装置の製造方法 |
US6103592A (en) * | 1997-05-01 | 2000-08-15 | International Business Machines Corp. | Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas |
JP3519579B2 (ja) * | 1997-09-09 | 2004-04-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
WO1999046081A1 (en) * | 1998-03-11 | 1999-09-16 | Strasbaugh | Multi-step chemical mechanical polishing process and device |
TW418459B (en) * | 1998-06-30 | 2001-01-11 | Fujitsu Ltd | Semiconductor device manufacturing method |
US6146975A (en) * | 1998-07-10 | 2000-11-14 | Lucent Technologies Inc. | Shallow trench isolation |
KR20010004309A (ko) * | 1999-06-28 | 2001-01-15 | 김영환 | 웨이퍼 정렬키 형성방법 |
KR100318270B1 (ko) * | 1999-12-16 | 2001-12-24 | 박종섭 | 반도체 소자의 오버레이 버어니어 형성방법 |
US6417072B2 (en) * | 2000-02-10 | 2002-07-09 | International Business Machines Corporation | Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step |
JP3503888B2 (ja) * | 2000-09-01 | 2004-03-08 | 沖電気工業株式会社 | アライメントマーク及びその形成方法 |
US6713884B2 (en) * | 2001-12-20 | 2004-03-30 | Infineon Technologies Ag | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors |
-
2002
- 2002-03-29 US US10/112,014 patent/US6627510B1/en not_active Expired - Lifetime
-
2003
- 2003-01-23 TW TW092101505A patent/TWI235450B/zh not_active IP Right Cessation
- 2003-02-07 KR KR10-2003-0007697A patent/KR100515181B1/ko not_active IP Right Cessation
- 2003-03-10 EP EP03251430A patent/EP1353369B1/de not_active Expired - Lifetime
- 2003-03-10 DE DE60317963T patent/DE60317963T2/de not_active Expired - Lifetime
- 2003-03-18 CN CNB031216234A patent/CN1278407C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1353369A3 (de) | 2004-05-06 |
CN1457090A (zh) | 2003-11-19 |
EP1353369B1 (de) | 2007-12-12 |
TW200304686A (en) | 2003-10-01 |
EP1353369A2 (de) | 2003-10-15 |
DE60317963T2 (de) | 2008-11-27 |
CN1278407C (zh) | 2006-10-04 |
TWI235450B (en) | 2005-07-01 |
KR20030078637A (ko) | 2003-10-08 |
US6627510B1 (en) | 2003-09-30 |
KR100515181B1 (ko) | 2005-09-16 |
US20030186503A1 (en) | 2003-10-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |