DE60233377D1 - Pegelschieber - Google Patents

Pegelschieber

Info

Publication number
DE60233377D1
DE60233377D1 DE60233377T DE60233377T DE60233377D1 DE 60233377 D1 DE60233377 D1 DE 60233377D1 DE 60233377 T DE60233377 T DE 60233377T DE 60233377 T DE60233377 T DE 60233377T DE 60233377 D1 DE60233377 D1 DE 60233377D1
Authority
DE
Germany
Prior art keywords
level shifter
shifter
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60233377T
Other languages
English (en)
Inventor
Tsuboi Hiroyoshi
Okuyama Yoshiaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60233377D1 publication Critical patent/DE60233377D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
DE60233377T 2001-11-28 2002-10-14 Pegelschieber Expired - Lifetime DE60233377D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001362490 2001-11-28
JP2002145080A JP3813538B2 (ja) 2001-11-28 2002-05-20 レベルシフタ

Publications (1)

Publication Number Publication Date
DE60233377D1 true DE60233377D1 (de) 2009-10-01

Family

ID=26624736

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60233377T Expired - Lifetime DE60233377D1 (de) 2001-11-28 2002-10-14 Pegelschieber

Country Status (7)

Country Link
US (1) US6774673B2 (de)
EP (1) EP1317066B1 (de)
JP (1) JP3813538B2 (de)
KR (1) KR100839551B1 (de)
CN (1) CN1242475C (de)
DE (1) DE60233377D1 (de)
TW (1) TW571514B (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6683486B2 (en) * 2002-04-02 2004-01-27 Infineon Technologies Ag Low voltage shifter with latching function
US6954100B2 (en) * 2003-09-12 2005-10-11 Freescale Semiconductor, Inc. Level shifter
US7276953B1 (en) 2003-11-12 2007-10-02 Cypress Semiconductor Corporation Level shifting input buffer circuit
JP4113491B2 (ja) * 2003-12-15 2008-07-09 三菱電機株式会社 半導体装置
US20050174158A1 (en) * 2004-02-06 2005-08-11 Khan Qadeer A. Bidirectional level shifter
JP4356836B2 (ja) * 2004-02-13 2009-11-04 川崎マイクロエレクトロニクス株式会社 レベルシフト回路
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
JP4127232B2 (ja) * 2004-04-01 2008-07-30 セイコーエプソン株式会社 レベルシフタ、レベルシフト回路、電気光学装置、及び電子機器
US7009424B2 (en) * 2004-06-10 2006-03-07 Freescale Semiconductor, Inc Single supply level shifter
US7102410B2 (en) * 2004-06-10 2006-09-05 Freescale Semiconductor, Inc. High voltage level converter using low voltage devices
US20050285658A1 (en) * 2004-06-29 2005-12-29 Schulmeyer Kyle C Level shifter with reduced duty cycle variation
US7151400B2 (en) * 2004-07-13 2006-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Boost-biased level shifter
US7956641B1 (en) 2005-04-28 2011-06-07 Cypress Semiconductor Corporation Low voltage interface circuit
US7286417B2 (en) * 2005-06-21 2007-10-23 Micron Technology, Inc. Low power dissipation voltage generator
US7312636B2 (en) * 2006-02-06 2007-12-25 Mosaid Technologies Incorporated Voltage level shifter circuit
KR100780769B1 (ko) * 2006-06-29 2007-11-30 주식회사 하이닉스반도체 듀얼 패스 레벨 시프터회로
KR101230313B1 (ko) * 2006-07-05 2013-02-06 재단법인서울대학교산학협력재단 레벨 시프터 및 그의 구동 방법
JP2008152845A (ja) * 2006-12-15 2008-07-03 Toshiba Corp 半導体記憶装置
TWI346453B (en) 2007-12-17 2011-08-01 Richtek Technology Corp Level shift circuit and method for the same
US7683668B1 (en) 2008-11-05 2010-03-23 Freescale Semiconductor, Inc. Level shifter
US8427888B2 (en) * 2010-02-09 2013-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Word-line driver using level shifter at local control circuit
WO2011132023A1 (en) * 2010-04-22 2011-10-27 Freescale Semiconductor, Inc. Voltage level shifter, decoupler for a voltage level shifter, and voltage shifting method
US8299725B2 (en) * 2010-07-06 2012-10-30 Himax Technologies Limited Driver for driving light emitting device
US8847870B2 (en) * 2011-10-27 2014-09-30 Citizen Finetech Miyota Co., Ltd. Voltage conversion apparatus suitable for a pixel driver and methods
US8787109B2 (en) * 2012-05-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Word line driver having a control switch
KR101745753B1 (ko) * 2013-06-21 2017-06-13 매그나칩 반도체 유한회사 다중 전원용 레벨 시프터
KR102290171B1 (ko) 2015-01-13 2021-08-17 주식회사 실리콘웍스 개선된 시간 응답 특성을 가지는 레벨 시프터 회로 및 그 제어 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433271A3 (en) * 1985-07-22 1991-11-06 Hitachi, Ltd. Semiconductor device
KR950004745B1 (ko) * 1990-01-23 1995-05-06 니뽄 덴끼 가부시끼가이샤 반도체 디지탈 회로
US5467038A (en) * 1994-02-15 1995-11-14 Hewlett-Packard Company Quick resolving latch
US5825225A (en) * 1996-02-09 1998-10-20 Intel Corporation Boosted differential latch
JP3859766B2 (ja) * 1996-05-24 2006-12-20 株式会社ルネサステクノロジ 半導体記憶装置の入力回路

Also Published As

Publication number Publication date
JP2003229756A (ja) 2003-08-15
US6774673B2 (en) 2004-08-10
EP1317066B1 (de) 2009-08-19
JP3813538B2 (ja) 2006-08-23
EP1317066A1 (de) 2003-06-04
CN1242475C (zh) 2006-02-15
TW571514B (en) 2004-01-11
KR100839551B1 (ko) 2008-06-20
KR20030043626A (ko) 2003-06-02
CN1423332A (zh) 2003-06-11
US20030098711A1 (en) 2003-05-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE