DE60216646D1 - Verfahren zur Herstellung eines monokristallinen Substrats und integrierter Schaltkreis mit einem solchen Substrat - Google Patents
Verfahren zur Herstellung eines monokristallinen Substrats und integrierter Schaltkreis mit einem solchen SubstratInfo
- Publication number
- DE60216646D1 DE60216646D1 DE60216646T DE60216646T DE60216646D1 DE 60216646 D1 DE60216646 D1 DE 60216646D1 DE 60216646 T DE60216646 T DE 60216646T DE 60216646 T DE60216646 T DE 60216646T DE 60216646 D1 DE60216646 D1 DE 60216646D1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- producing
- integrated circuit
- monocrystalline
- monocrystalline substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0100414A FR2819631B1 (fr) | 2001-01-12 | 2001-01-12 | Procede de fabrication d'un substrat monocristallin, et circuit integre comportant un tel substrat |
FR0100414 | 2001-01-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60216646D1 true DE60216646D1 (de) | 2007-01-25 |
DE60216646T2 DE60216646T2 (de) | 2007-10-11 |
Family
ID=8858764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60216646T Expired - Lifetime DE60216646T2 (de) | 2001-01-12 | 2002-01-09 | Verfahren zur Herstellung eines monokristallinen Substrats und integrierter Schaltkreis mit einem solchen Substrat |
Country Status (5)
Country | Link |
---|---|
US (1) | US7060596B2 (de) |
EP (1) | EP1223614B1 (de) |
JP (1) | JP2002270509A (de) |
DE (1) | DE60216646T2 (de) |
FR (1) | FR2819631B1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2819632B1 (fr) * | 2001-01-12 | 2003-09-26 | St Microelectronics Sa | Circuit integre comportant un dispositif analogique de stockage de charges, et procede de fabrication |
US6784072B2 (en) * | 2002-07-22 | 2004-08-31 | International Business Machines Corporation | Control of buried oxide in SIMOX |
FR3099964B1 (fr) * | 2019-08-14 | 2024-03-29 | St Microelectronics Crolles 2 Sas | Procédé de réalisation d’une électrode dans un substrat de base et dispositif électronique |
CN112768509B (zh) * | 2021-02-03 | 2022-07-08 | 杭州中瑞宏芯半导体有限公司 | 一种反向恢复时间短的frd二极管及制备方法 |
CN117568912A (zh) * | 2023-11-21 | 2024-02-20 | 松山湖材料实验室 | 一种单晶复合衬底及其制备方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292365A (ja) * | 1985-10-18 | 1987-04-27 | Fuji Photo Film Co Ltd | 半導体装置およびその製造方法 |
US4649625A (en) * | 1985-10-21 | 1987-03-17 | International Business Machines Corporation | Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor |
JPS62293759A (ja) * | 1986-06-13 | 1987-12-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US4942554A (en) * | 1987-11-26 | 1990-07-17 | Siemens Aktiengesellschaft | Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same |
KR100197648B1 (ko) * | 1995-08-26 | 1999-06-15 | 김영환 | 반도체소자의 소자분리 절연막 형성방법 |
FR2756104B1 (fr) | 1996-11-19 | 1999-01-29 | Sgs Thomson Microelectronics | Fabrication de circuits integres bipolaires/cmos |
JP3502531B2 (ja) * | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US5891763A (en) * | 1997-10-22 | 1999-04-06 | Wanlass; Frank M. | Damascene pattering of SOI MOS transistors |
US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
US6074954A (en) * | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
US6214653B1 (en) * | 1999-06-04 | 2001-04-10 | International Business Machines Corporation | Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate |
FR2819636B1 (fr) * | 2001-01-12 | 2003-09-26 | St Microelectronics Sa | Circuit integre comportant un point memoire de type dram, et procede de fabrication |
-
2001
- 2001-01-12 FR FR0100414A patent/FR2819631B1/fr not_active Expired - Fee Related
- 2001-12-26 JP JP2001394184A patent/JP2002270509A/ja active Pending
-
2002
- 2002-01-09 EP EP02290038A patent/EP1223614B1/de not_active Expired - Lifetime
- 2002-01-09 DE DE60216646T patent/DE60216646T2/de not_active Expired - Lifetime
- 2002-01-11 US US10/044,402 patent/US7060596B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1223614A1 (de) | 2002-07-17 |
JP2002270509A (ja) | 2002-09-20 |
FR2819631A1 (fr) | 2002-07-19 |
US20020094678A1 (en) | 2002-07-18 |
EP1223614B1 (de) | 2006-12-13 |
US7060596B2 (en) | 2006-06-13 |
FR2819631B1 (fr) | 2003-04-04 |
DE60216646T2 (de) | 2007-10-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |