DE602008003345D1 - Halbleiterspeicher, Speichersteuerung, System und Betriebsverfahren für einen Halbleiterspeicher - Google Patents

Halbleiterspeicher, Speichersteuerung, System und Betriebsverfahren für einen Halbleiterspeicher

Info

Publication number
DE602008003345D1
DE602008003345D1 DE602008003345T DE602008003345T DE602008003345D1 DE 602008003345 D1 DE602008003345 D1 DE 602008003345D1 DE 602008003345 T DE602008003345 T DE 602008003345T DE 602008003345 T DE602008003345 T DE 602008003345T DE 602008003345 D1 DE602008003345 D1 DE 602008003345D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory
operating method
control
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008003345T
Other languages
English (en)
Inventor
Kuninori Kawabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602008003345D1 publication Critical patent/DE602008003345D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE602008003345T 2007-03-16 2008-02-27 Halbleiterspeicher, Speichersteuerung, System und Betriebsverfahren für einen Halbleiterspeicher Active DE602008003345D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007068682A JP5157207B2 (ja) 2007-03-16 2007-03-16 半導体メモリ、メモリコントローラ、システムおよび半導体メモリの動作方法

Publications (1)

Publication Number Publication Date
DE602008003345D1 true DE602008003345D1 (de) 2010-12-23

Family

ID=39476074

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008003345T Active DE602008003345D1 (de) 2007-03-16 2008-02-27 Halbleiterspeicher, Speichersteuerung, System und Betriebsverfahren für einen Halbleiterspeicher

Country Status (6)

Country Link
US (1) US7675800B2 (de)
EP (2) EP2284838B1 (de)
JP (1) JP5157207B2 (de)
KR (1) KR100918470B1 (de)
CN (1) CN101266833B (de)
DE (1) DE602008003345D1 (de)

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* Cited by examiner, † Cited by third party
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JP4843655B2 (ja) * 2008-09-24 2011-12-21 株式会社東芝 半導体記憶装置
JP2011018417A (ja) * 2009-07-10 2011-01-27 Renesas Electronics Corp 半導体記憶装置及び半導体記憶装置のリフレッシュ制御方法
JP2011018427A (ja) * 2009-07-10 2011-01-27 Renesas Electronics Corp 半導体記憶装置
CN101894584B (zh) * 2010-06-12 2013-01-16 苏州国芯科技有限公司 一种动态随机存储器读写模式信号时序参数的实现方法
US8533538B2 (en) 2010-06-28 2013-09-10 Intel Corporation Method and apparatus for training a memory signal via an error signal of a memory
KR101212738B1 (ko) 2010-10-29 2012-12-14 에스케이하이닉스 주식회사 리프레쉬 제어회로 및 이를 포함하는 반도체 메모리 장치 및 리프레쉬 제어방법
CN102034526B (zh) * 2010-12-17 2013-06-12 曙光信息产业股份有限公司 一种用fpga实现的sdram刷新的方法
US8687450B2 (en) * 2011-02-28 2014-04-01 SK Hynix Inc. Semiconductor device
CN103035283B (zh) * 2011-09-29 2016-09-07 复旦大学 一种不含温度传感器的多级温度控制自刷新存储设备及其方法
CN102426850A (zh) * 2011-12-13 2012-04-25 曙光信息产业(北京)有限公司 一种减少ddr2初始化时间的方法
US9141561B2 (en) * 2012-10-25 2015-09-22 Texas Instruments Incorporated Master circuits having dynamic priority leads coupled with memory controller
CN103236271A (zh) * 2013-03-26 2013-08-07 深圳市国微电子有限公司 基于三模冗余加固单粒子翻转的存储器、加固方法
US9177626B2 (en) * 2013-08-27 2015-11-03 Naoki Shimizu Semiconductor memory device
US9201728B2 (en) * 2013-09-12 2015-12-01 Seagate Technology Llc Memory device with variable code rate
KR20150064953A (ko) * 2013-12-04 2015-06-12 에스케이하이닉스 주식회사 반도체 메모리 장치
US9928895B2 (en) * 2016-02-03 2018-03-27 Samsung Electronics Co., Ltd. Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof
US9892778B1 (en) * 2016-12-15 2018-02-13 SK Hynix Inc. Memory device, memory system including the same, operation method of the memory system
US10141041B1 (en) * 2017-11-01 2018-11-27 Micron Technology, Inc. Systems and methods for maintaining refresh operations of memory banks using a shared
US10910033B2 (en) * 2018-12-14 2021-02-02 Micron Technology, Inc. Refresh-related activation in memory
JP6894459B2 (ja) 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリとその動作方法

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IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
KR900007998B1 (ko) * 1985-10-29 1990-10-23 후지쓰 가부시끼가이샤 분할된 메모리 셀 어레이를 갖는 반도체 기판상에 형성된 랜덤 액세스 메모리
US5469559A (en) * 1993-07-06 1995-11-21 Dell Usa, L.P. Method and apparatus for refreshing a selected portion of a dynamic random access memory
JPH08138374A (ja) * 1994-11-10 1996-05-31 Nec Corp 半導体メモリ装置およびそのリフレッシュ方法
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US6298413B1 (en) * 1998-11-19 2001-10-02 Micron Technology, Inc. Apparatus for controlling refresh of a multibank memory device
JP2001332084A (ja) * 2000-05-22 2001-11-30 Fujitsu Ltd 半導体記憶装置及び半導体記憶装置のリフレッシュ方法
JP2002008370A (ja) * 2000-06-21 2002-01-11 Mitsubishi Electric Corp 半導体記憶装置
JP4641094B2 (ja) * 2000-11-17 2011-03-02 富士通セミコンダクター株式会社 半導体メモリ
JP4768163B2 (ja) 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 半導体メモリ
JP4597470B2 (ja) * 2002-07-25 2010-12-15 富士通セミコンダクター株式会社 半導体メモリ
CN2711801Y (zh) * 2003-12-19 2005-07-20 中国科学院长春光学精密机械与物理研究所 一种刷新时序信号发生器
US6967885B2 (en) * 2004-01-15 2005-11-22 International Business Machines Corporation Concurrent refresh mode with distributed row address counters in an embedded DRAM
US20050268022A1 (en) 2004-05-26 2005-12-01 Pelley Perry H Cache line memory and method therefor
JP4912718B2 (ja) * 2006-03-30 2012-04-11 富士通セミコンダクター株式会社 ダイナミック型半導体メモリ
JP2008084426A (ja) * 2006-09-27 2008-04-10 Fujitsu Ltd 半導体メモリおよびシステム

Also Published As

Publication number Publication date
US7675800B2 (en) 2010-03-09
JP2008234699A (ja) 2008-10-02
US20080225619A1 (en) 2008-09-18
CN101266833A (zh) 2008-09-17
EP1970912A1 (de) 2008-09-17
EP2284838A1 (de) 2011-02-16
EP2284838B1 (de) 2015-02-18
CN101266833B (zh) 2011-04-06
KR100918470B1 (ko) 2009-09-24
KR20080084642A (ko) 2008-09-19
JP5157207B2 (ja) 2013-03-06
EP1970912B1 (de) 2010-11-10

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Legal Events

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