DE602006009212D1 - Gerät, System und Verfahren für einen Grafikspeicher-Hub - Google Patents

Gerät, System und Verfahren für einen Grafikspeicher-Hub

Info

Publication number
DE602006009212D1
DE602006009212D1 DE602006009212T DE602006009212T DE602006009212D1 DE 602006009212 D1 DE602006009212 D1 DE 602006009212D1 DE 602006009212 T DE602006009212 T DE 602006009212T DE 602006009212 T DE602006009212 T DE 602006009212T DE 602006009212 D1 DE602006009212 D1 DE 602006009212D1
Authority
DE
Germany
Prior art keywords
graphics memory
memory hub
hub
graphics
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006009212T
Other languages
English (en)
Inventor
Joseph David Greco
Jonah M Alben
Barry A Wagner
Anthony Michael Tamasi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of DE602006009212D1 publication Critical patent/DE602006009212D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE602006009212T 2005-12-15 2006-03-27 Gerät, System und Verfahren für einen Grafikspeicher-Hub Active DE602006009212D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/303,187 US7477257B2 (en) 2005-12-15 2005-12-15 Apparatus, system, and method for graphics memory hub

Publications (1)

Publication Number Publication Date
DE602006009212D1 true DE602006009212D1 (de) 2009-10-29

Family

ID=37719125

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006009212T Active DE602006009212D1 (de) 2005-12-15 2006-03-27 Gerät, System und Verfahren für einen Grafikspeicher-Hub

Country Status (6)

Country Link
US (2) US7477257B2 (de)
EP (1) EP1808772B1 (de)
JP (1) JP2007164755A (de)
CN (1) CN1983329B (de)
DE (1) DE602006009212D1 (de)
TW (1) TWI447672B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
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US20080036758A1 (en) * 2006-03-31 2008-02-14 Intelisum Inc. Systems and methods for determining a global or local position of a point of interest within a scene using a three-dimensional model of the scene
US7412554B2 (en) * 2006-06-15 2008-08-12 Nvidia Corporation Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units
US8207976B2 (en) * 2007-03-15 2012-06-26 Qimonda Ag Circuit
ATE537231T1 (de) * 2007-10-24 2011-12-15 Agfa Graphics Nv Strahlenhärtbare tintenstrahldruckfarben und tinten mit verbesserter vergilbungsbeständigkeit
US8391302B1 (en) * 2009-12-03 2013-03-05 Integrated Device Technology, Inc. High-performance ingress buffer for a packet switch
US10817043B2 (en) 2011-07-26 2020-10-27 Nvidia Corporation System and method for entering and exiting sleep mode in a graphics subsystem
CN102522113B (zh) * 2011-09-28 2014-09-17 华为技术有限公司 一种sdram桥接电路
US9086881B2 (en) * 2012-06-29 2015-07-21 Intel Corporation Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems
US9110795B2 (en) 2012-12-10 2015-08-18 Qualcomm Incorporated System and method for dynamically allocating memory in a memory subsystem having asymmetric memory components
US9092327B2 (en) 2012-12-10 2015-07-28 Qualcomm Incorporated System and method for allocating memory to dissimilar memory devices using quality of service
US8959298B2 (en) 2012-12-10 2015-02-17 Qualcomm Incorporated System and method for managing performance of a computing device having dissimilar memory types
US10062135B2 (en) * 2013-07-31 2018-08-28 National Technology & Engineering Solutions Of Sandia, Llc Graphics processing unit management system for computed tomography
US9383809B2 (en) * 2013-11-13 2016-07-05 Qualcomm Incorporated System and method for reducing memory I/O power via data masking
WO2016122480A1 (en) 2015-01-28 2016-08-04 Hewlett-Packard Development Company, L.P. Bidirectional lane routing
CN108933882B (zh) * 2017-05-24 2021-01-26 北京小米移动软件有限公司 相机模组及电子设备
US11127719B2 (en) 2020-01-23 2021-09-21 Nvidia Corporation Face-to-face dies with enhanced power delivery using extended TSVS
US11616023B2 (en) 2020-01-23 2023-03-28 Nvidia Corporation Face-to-face dies with a void for enhanced inductor performance
US11699662B2 (en) * 2020-01-23 2023-07-11 Nvidia Corporation Face-to-face dies with probe pads for pre-assembly testing

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212541A (ja) * 1988-04-29 1990-01-17 Internatl Business Mach Corp <Ibm> コンピユーテイング・システム及びその動作方法
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US6725349B2 (en) * 1994-12-23 2004-04-20 Intel Corporation Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
US7065050B1 (en) 1998-07-08 2006-06-20 Broadcom Corporation Apparatus and method for controlling data flow in a network switch
AU6311299A (en) 1998-07-08 2000-02-01 Broadcom Corporation Network switching architecture with multiple table synchronization, and forwarding of both IP and IPX packets
US6260127B1 (en) * 1998-07-13 2001-07-10 Compaq Computer Corporation Method and apparatus for supporting heterogeneous memory in computer systems
GB9828144D0 (en) 1998-12-22 1999-02-17 Power X Limited Data switching apparatus
US6449679B2 (en) * 1999-02-26 2002-09-10 Micron Technology, Inc. RAM controller interface device for RAM compatibility (memory translator hub)
US6567091B2 (en) * 2000-02-01 2003-05-20 Interactive Silicon, Inc. Video controller system with object display lists
US6502146B1 (en) * 2000-03-29 2002-12-31 Intel Corporation Apparatus and method for dedicated interconnection over a shared external bus
US6630936B1 (en) * 2000-09-28 2003-10-07 Intel Corporation Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel
US6532525B1 (en) * 2000-09-29 2003-03-11 Ati Technologies, Inc. Method and apparatus for accessing memory
US6792516B2 (en) * 2001-12-28 2004-09-14 Intel Corporation Memory arbiter with intelligent page gathering logic
US6954811B2 (en) 2002-07-19 2005-10-11 Calix Networks, Inc. Arbiter for an input buffered communication switch
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US20070067517A1 (en) * 2005-09-22 2007-03-22 Tzu-Jen Kuo Integrated physics engine and related graphics processing system

Also Published As

Publication number Publication date
CN1983329A (zh) 2007-06-20
EP1808772A1 (de) 2007-07-18
JP2007164755A (ja) 2007-06-28
US20070139426A1 (en) 2007-06-21
TW200723161A (en) 2007-06-16
US8194085B2 (en) 2012-06-05
CN1983329B (zh) 2011-10-19
EP1808772B1 (de) 2009-09-16
US7477257B2 (en) 2009-01-13
US20090079748A1 (en) 2009-03-26
TWI447672B (zh) 2014-08-01

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