DE602006014987D1 - Verfahren zur gesteuerten programmierung von nichtflüchtigem speicher, der bitleitungskopplung aufweist - Google Patents

Verfahren zur gesteuerten programmierung von nichtflüchtigem speicher, der bitleitungskopplung aufweist

Info

Publication number
DE602006014987D1
DE602006014987D1 DE602006014987T DE602006014987T DE602006014987D1 DE 602006014987 D1 DE602006014987 D1 DE 602006014987D1 DE 602006014987 T DE602006014987 T DE 602006014987T DE 602006014987 T DE602006014987 T DE 602006014987T DE 602006014987 D1 DE602006014987 D1 DE 602006014987D1
Authority
DE
Germany
Prior art keywords
bit line
voltage
select gate
bit
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006014987T
Other languages
English (en)
Inventor
Jeffrey W Lutze
Yan Li
Siu L Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/250,735 external-priority patent/US7286406B2/en
Priority claimed from US11/251,458 external-priority patent/US7206235B1/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of DE602006014987D1 publication Critical patent/DE602006014987D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE602006014987T 2005-10-14 2006-10-11 Verfahren zur gesteuerten programmierung von nichtflüchtigem speicher, der bitleitungskopplung aufweist Active DE602006014987D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/250,735 US7286406B2 (en) 2005-10-14 2005-10-14 Method for controlled programming of non-volatile memory exhibiting bit line coupling
US11/251,458 US7206235B1 (en) 2005-10-14 2005-10-14 Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
PCT/US2006/039636 WO2007047283A1 (en) 2005-10-14 2006-10-11 Method for controlled programming of non-volatile memory exhibiting bit line coupling

Publications (1)

Publication Number Publication Date
DE602006014987D1 true DE602006014987D1 (de) 2010-07-29

Family

ID=37726848

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006014987T Active DE602006014987D1 (de) 2005-10-14 2006-10-11 Verfahren zur gesteuerten programmierung von nichtflüchtigem speicher, der bitleitungskopplung aufweist

Country Status (7)

Country Link
EP (1) EP1946324B1 (de)
JP (1) JP4723000B2 (de)
KR (1) KR100966358B1 (de)
AT (1) ATE471563T1 (de)
DE (1) DE602006014987D1 (de)
TW (1) TWI315069B (de)
WO (1) WO2007047283A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101407361B1 (ko) * 2008-04-14 2014-06-13 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 프로그램 방법
KR101490426B1 (ko) * 2008-11-14 2015-02-06 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법
US8737129B2 (en) 2008-11-14 2014-05-27 Samsung Electronics Co., Ltd. Nonvolatile memory device and read method thereof
US8169822B2 (en) * 2009-11-11 2012-05-01 Sandisk Technologies Inc. Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
US8310870B2 (en) 2010-08-03 2012-11-13 Sandisk Technologies Inc. Natural threshold voltage distribution compaction in non-volatile memory
US9711211B2 (en) 2015-10-29 2017-07-18 Sandisk Technologies Llc Dynamic threshold voltage compaction for non-volatile memory
KR102493068B1 (ko) * 2020-10-13 2023-01-30 한양대학교 산학협력단 듀얼 게이트 구조의 3차원 플래시 메모리 및 그 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910007434B1 (ko) * 1988-12-15 1991-09-26 삼성전자 주식회사 전기적으로 소거 및 프로그램 가능한 반도체 메모리장치 및 그 소거 및 프로그램 방법
JP4157189B2 (ja) * 1997-05-14 2008-09-24 株式会社東芝 不揮発性半導体記憶装置
JP3679970B2 (ja) * 2000-03-28 2005-08-03 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP3810985B2 (ja) * 2000-05-22 2006-08-16 株式会社東芝 不揮発性半導体メモリ
JP4732084B2 (ja) * 2004-09-21 2011-07-27 三星モバイルディスプレイ株式會社 発光素子用の基板、その製造方法、発光素子用の電極、及びこれを備えた発光素子

Also Published As

Publication number Publication date
WO2007047283A1 (en) 2007-04-26
EP1946324B1 (de) 2010-06-16
JP2009512115A (ja) 2009-03-19
TW200733119A (en) 2007-09-01
KR20080084923A (ko) 2008-09-22
ATE471563T1 (de) 2010-07-15
KR100966358B1 (ko) 2010-06-28
TWI315069B (en) 2009-09-21
JP4723000B2 (ja) 2011-07-13
EP1946324A1 (de) 2008-07-23

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