DE602006007334D1 - Konfigurationsfinalisierung beim ersten gültigen nand-befehl - Google Patents

Konfigurationsfinalisierung beim ersten gültigen nand-befehl

Info

Publication number
DE602006007334D1
DE602006007334D1 DE602006007334T DE602006007334T DE602006007334D1 DE 602006007334 D1 DE602006007334 D1 DE 602006007334D1 DE 602006007334 T DE602006007334 T DE 602006007334T DE 602006007334 T DE602006007334 T DE 602006007334T DE 602006007334 D1 DE602006007334 D1 DE 602006007334D1
Authority
DE
Germany
Prior art keywords
finalization
configuration
startup
receipt
valid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006007334T
Other languages
English (en)
Inventor
Frankie F Roohparvar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE602006007334D1 publication Critical patent/DE602006007334D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Read Only Memory (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
DE602006007334T 2005-04-29 2006-04-28 Konfigurationsfinalisierung beim ersten gültigen nand-befehl Active DE602006007334D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/119,321 US8103805B2 (en) 2005-04-29 2005-04-29 Configuration finalization on first valid NAND command
PCT/US2006/016223 WO2006119017A1 (en) 2005-04-29 2006-04-28 Configuration finalization on first valid nand command

Publications (1)

Publication Number Publication Date
DE602006007334D1 true DE602006007334D1 (de) 2009-07-30

Family

ID=36872831

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006007334T Active DE602006007334D1 (de) 2005-04-29 2006-04-28 Konfigurationsfinalisierung beim ersten gültigen nand-befehl

Country Status (9)

Country Link
US (2) US8103805B2 (de)
EP (1) EP1875474B1 (de)
JP (1) JP4655244B2 (de)
KR (1) KR100936849B1 (de)
CN (1) CN101194319B (de)
AT (1) ATE434256T1 (de)
DE (1) DE602006007334D1 (de)
TW (1) TWI312463B (de)
WO (1) WO2006119017A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150025782A (ko) * 2013-08-30 2015-03-11 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 컴퓨터 시스템
KR20160139495A (ko) * 2015-05-27 2016-12-07 에스케이하이닉스 주식회사 초기화 동작을 수행하는 반도체장치 및 반도체시스템

Family Cites Families (26)

* Cited by examiner, † Cited by third party
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US5333300A (en) * 1991-02-11 1994-07-26 Intel Corporation Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory
US5469553A (en) * 1992-04-16 1995-11-21 Quantum Corporation Event driven power reducing software state machine
US5463336A (en) * 1994-01-27 1995-10-31 Rockwell International Corporation Supply sensing power-on reset circuit
US5737612A (en) * 1994-09-30 1998-04-07 Cypress Semiconductor Corp. Power-on reset control circuit
JPH10228768A (ja) * 1997-02-14 1998-08-25 Mitsubishi Electric Corp 半導体記憶装置
JPH10334689A (ja) * 1997-05-30 1998-12-18 Fujitsu Ltd 半導体記憶装置
JPH1116395A (ja) * 1997-06-25 1999-01-22 Mitsubishi Electric Corp 半導体記憶装置
JP4060442B2 (ja) 1998-05-28 2008-03-12 富士通株式会社 メモリデバイス
US6263399B1 (en) * 1998-06-01 2001-07-17 Sun Microsystems, Inc. Microprocessor to NAND flash interface
JP2000030446A (ja) 1998-07-13 2000-01-28 Mitsubishi Electric Corp 半導体記憶装置のデフォルト動作モード設定変更回路
US6084803A (en) * 1998-10-23 2000-07-04 Mosel Vitelic, Inc. Initialization of non-volatile programmable latches in circuits in which an initialization operation is performed
JP2000149522A (ja) * 1998-11-09 2000-05-30 Sony Corp サーバー及び該サーバーに搭載されるｈｄｄ装置
JP3695966B2 (ja) * 1998-11-13 2005-09-14 松下電器産業株式会社 半導体集積回路
US6393527B1 (en) * 1998-12-18 2002-05-21 Ati International Srl Prefetch buffer with continue detect
JP3371845B2 (ja) * 1999-03-26 2003-01-27 日本電気株式会社 モード設定確定信号生成回路及び半導体記憶装置
JP2002009601A (ja) * 2000-06-27 2002-01-11 Fujitsu Ltd 半導体集積回路および半導体集積回路の初期化方法
US6603344B2 (en) * 2001-07-11 2003-08-05 Infineon Technologies Ag Zero static power programmable fuse cell for integrated circuits
US6901018B2 (en) * 2001-07-18 2005-05-31 Samsung Electronics Co, Ltd. Method of generating initializing signal in semiconductor memory device
DE10232859B4 (de) * 2001-07-18 2014-11-13 Samsung Electronics Co., Ltd. Verfahren zur Erzeugung eines Initialisierungssignals
US7036004B2 (en) * 2001-07-25 2006-04-25 Micron Technology, Inc. Power up initialization for memory
US6744274B1 (en) * 2001-08-09 2004-06-01 Stretch, Inc. Programmable logic core adapter
ITRM20010522A1 (it) * 2001-08-30 2003-02-28 Micron Technology Inc Sequenziale di "power-on-reset" condizionato e robusto a potenza ultrabassa per circuiti integrati.
US6943596B2 (en) * 2002-03-12 2005-09-13 Broadcom Corporation Power-on reset circuit for use in low power supply voltage applications
KR100463201B1 (ko) * 2002-05-28 2004-12-23 삼성전자주식회사 파워 검출 회로, 이를 이용한 플래시 메모리 장치, 그 플래시 메모리 장치의 파워-온 독출 신호 발생 방법 및 플래시 메모리 장치의 안정적인 파워-온 독출 방법
JP3990269B2 (ja) * 2002-12-17 2007-10-10 株式会社東芝 半導体装置及びその起動方法
JP4138521B2 (ja) * 2003-02-13 2008-08-27 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
TWI312463B (en) 2009-07-21
US8862788B2 (en) 2014-10-14
ATE434256T1 (de) 2009-07-15
WO2006119017A1 (en) 2006-11-09
TW200638196A (en) 2006-11-01
US20120113727A1 (en) 2012-05-10
CN101194319A (zh) 2008-06-04
CN101194319B (zh) 2010-08-11
US20060291280A1 (en) 2006-12-28
EP1875474B1 (de) 2009-06-17
JP2008539535A (ja) 2008-11-13
EP1875474A1 (de) 2008-01-09
KR100936849B1 (ko) 2010-01-14
JP4655244B2 (ja) 2011-03-23
KR20080009306A (ko) 2008-01-28
US8103805B2 (en) 2012-01-24

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Legal Events

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8364 No opposition during term of opposition