WO2009019788A1 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
WO2009019788A1
WO2009019788A1 PCT/JP2007/065640 JP2007065640W WO2009019788A1 WO 2009019788 A1 WO2009019788 A1 WO 2009019788A1 JP 2007065640 W JP2007065640 W JP 2007065640W WO 2009019788 A1 WO2009019788 A1 WO 2009019788A1
Authority
WO
WIPO (PCT)
Prior art keywords
switching means
voltage
integrated circuit
semiconductor integrated
processor
Prior art date
Application number
PCT/JP2007/065640
Other languages
English (en)
French (fr)
Inventor
Motohisa Ikeda
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/065640 priority Critical patent/WO2009019788A1/ja
Priority to JP2009526315A priority patent/JP5333219B2/ja
Priority to EP07792290.4A priority patent/EP2178115B1/en
Publication of WO2009019788A1 publication Critical patent/WO2009019788A1/ja
Priority to US12/688,499 priority patent/US8022753B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)

Abstract

　本発明は、プロセッサブロックとプロセッサ以外の論理演算ブロックを有しており間欠動作を行う半導体集積回路において、前記プロセッサ以外の論理演算ブロックに通常動作用電圧を供給する第１のスイッチ手段と、前記プロセッサブロックに通常動作用電圧を供給する第２のスイッチ手段と、前記プロセッサブロックに前記通常動作用電圧より低いデータ保持用電圧を供給するための第３のスイッチ手段と、前記第２のスイッチ手段がオフで前記第３のスイッチ手段がオンしているときにオンして前記プロセッサブロックに前記データ保持用電圧を供給する第４のスイッチ手段とを有する。
PCT/JP2007/065640 2007-08-09 2007-08-09 半導体集積回路 WO2009019788A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/065640 WO2009019788A1 (ja) 2007-08-09 2007-08-09 半導体集積回路
JP2009526315A JP5333219B2 (ja) 2007-08-09 2007-08-09 半導体集積回路
EP07792290.4A EP2178115B1 (en) 2007-08-09 2007-08-09 Semiconductor integrated circuit
US12/688,499 US8022753B2 (en) 2007-08-09 2010-01-15 Semiconductor integrated circuit with intermittent power supply operation of circuit blocks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/065640 WO2009019788A1 (ja) 2007-08-09 2007-08-09 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/688,499 Continuation US8022753B2 (en) 2007-08-09 2010-01-15 Semiconductor integrated circuit with intermittent power supply operation of circuit blocks

Publications (1)

Publication Number Publication Date
WO2009019788A1 true WO2009019788A1 (ja) 2009-02-12

Family

ID=40341036

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/065640 WO2009019788A1 (ja) 2007-08-09 2007-08-09 半導体集積回路

Country Status (4)

Country Link
US (1) US8022753B2 (ja)
EP (1) EP2178115B1 (ja)
JP (1) JP5333219B2 (ja)
WO (1) WO2009019788A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859600A (zh) * 2009-04-03 2010-10-13 台湾积体电路制造股份有限公司 集成电路结构
JP2010251445A (ja) * 2009-04-14 2010-11-04 Hitachi Ltd 半導体装置およびそれを用いた情報処理装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8411525B2 (en) 2010-04-29 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits having a diode-connected transistor with back-biased control
FR2967797A1 (fr) * 2010-11-18 2012-05-25 St Microelectronics Sa Systeme et procede d'alimentation d'un composant par exemple un processeur
US9166567B2 (en) * 2013-03-15 2015-10-20 University Of California, San Diego Data-retained power-gating circuit and devices including the same
US9350332B1 (en) * 2015-02-11 2016-05-24 SK Hynix Inc. Semiconductor device including retention circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175909A (ja) * 1987-01-16 1988-07-20 Nec Corp １チツプマイクロコンピユ−タ
JPH05108850A (ja) * 1991-10-15 1993-04-30 Nec Kyushu Ltd １チツプマイクロコンピユータ
JP2003114742A (ja) 2001-10-04 2003-04-18 Matsushita Electric Ind Co Ltd 電源遮断制御装置
JP2006127152A (ja) * 2004-10-28 2006-05-18 Fujitsu Ltd 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3549602B2 (ja) * 1995-01-12 2004-08-04 株式会社ルネサステクノロジ 半導体記憶装置
KR100269643B1 (ko) * 1997-11-27 2000-10-16 김영환 전력소비 억제회로
DE10120790A1 (de) * 2001-04-27 2002-11-21 Infineon Technologies Ag Schaltungsanordnung zur Verringerung der Versorgungsspannung eines Schaltungsteils sowie Verfahren zum Aktivieren eines Schaltungsteils
JP4082706B2 (ja) * 2005-04-12 2008-04-30 学校法人早稲田大学 マルチプロセッサシステム及びマルチグレイン並列化コンパイラ
JP2006318380A (ja) * 2005-05-16 2006-11-24 Handotai Rikougaku Kenkyu Center:Kk 回路システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63175909A (ja) * 1987-01-16 1988-07-20 Nec Corp １チツプマイクロコンピユ−タ
JPH05108850A (ja) * 1991-10-15 1993-04-30 Nec Kyushu Ltd １チツプマイクロコンピユータ
JP2003114742A (ja) 2001-10-04 2003-04-18 Matsushita Electric Ind Co Ltd 電源遮断制御装置
JP2006127152A (ja) * 2004-10-28 2006-05-18 Fujitsu Ltd 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859600A (zh) * 2009-04-03 2010-10-13 台湾积体电路制造股份有限公司 集成电路结构
JP2010263194A (ja) * 2009-04-03 2010-11-18 Taiwan Semiconductor Manufacturing Co Ltd 集積回路構造
JP2010251445A (ja) * 2009-04-14 2010-11-04 Hitachi Ltd 半導体装置およびそれを用いた情報処理装置

Also Published As

Publication number Publication date
US8022753B2 (en) 2011-09-20
EP2178115A1 (en) 2010-04-21
JP5333219B2 (ja) 2013-11-06
EP2178115B1 (en) 2017-12-13
EP2178115A4 (en) 2011-01-26
US20100117714A1 (en) 2010-05-13
JPWO2009019788A1 (ja) 2010-10-28

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