DE602006006545D1 - Dynamischer Halbleiterspeicher mit Reduzierung der Häufigkeit von Aktualisierungsbefehlsanfragen und Aktualisierungssteuerverfahren dafür - Google Patents
Dynamischer Halbleiterspeicher mit Reduzierung der Häufigkeit von Aktualisierungsbefehlsanfragen und Aktualisierungssteuerverfahren dafürInfo
- Publication number
- DE602006006545D1 DE602006006545D1 DE602006006545T DE602006006545T DE602006006545D1 DE 602006006545 D1 DE602006006545 D1 DE 602006006545D1 DE 602006006545 T DE602006006545 T DE 602006006545T DE 602006006545 T DE602006006545 T DE 602006006545T DE 602006006545 D1 DE602006006545 D1 DE 602006006545D1
- Authority
- DE
- Germany
- Prior art keywords
- update
- reduction
- frequency
- semiconductor memory
- control methods
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006093827A JP4912718B2 (ja) | 2006-03-30 | 2006-03-30 | ダイナミック型半導体メモリ |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602006006545D1 true DE602006006545D1 (de) | 2009-06-10 |
Family
ID=36950494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602006006545T Active DE602006006545D1 (de) | 2006-03-30 | 2006-06-12 | Dynamischer Halbleiterspeicher mit Reduzierung der Häufigkeit von Aktualisierungsbefehlsanfragen und Aktualisierungssteuerverfahren dafür |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7630268B2 (enExample) |
| EP (1) | EP1840900B1 (enExample) |
| JP (1) | JP4912718B2 (enExample) |
| KR (1) | KR100868713B1 (enExample) |
| CN (1) | CN101047025B (enExample) |
| DE (1) | DE602006006545D1 (enExample) |
| TW (1) | TWI312515B (enExample) |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5157207B2 (ja) * | 2007-03-16 | 2013-03-06 | 富士通セミコンダクター株式会社 | 半導体メモリ、メモリコントローラ、システムおよび半導体メモリの動作方法 |
| JP2008262616A (ja) * | 2007-04-10 | 2008-10-30 | Matsushita Electric Ind Co Ltd | 半導体記憶装置、内部リフレッシュ停止方法、外部アクセスと内部リフレッシュとの競合処理方法、カウンタ初期化手法、外部リフレッシュのリフレッシュアドレス検出方法、及び外部リフレッシュ実行選択方法 |
| US8310893B2 (en) * | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
| WO2012095901A1 (ja) * | 2011-01-12 | 2012-07-19 | パナソニック株式会社 | プログラム実行装置およびコンパイラシステム |
| FR2980904A1 (fr) * | 2011-09-30 | 2013-04-05 | St Microelectronics Crolles 2 | Procede de commande d'un circuit electronique integrant au moins une matrice dram |
| US11024352B2 (en) | 2012-04-10 | 2021-06-01 | Samsung Electronics Co., Ltd. | Memory system for access concentration decrease management and access concentration decrease method |
| WO2014002222A1 (ja) * | 2012-06-28 | 2014-01-03 | 三菱電機株式会社 | リードリクエスト処理装置 |
| KR20150017276A (ko) | 2013-08-06 | 2015-02-16 | 삼성전자주식회사 | 리프레쉬 레버리징 효율을 향상시키는 휘발성 메모리 장치의 리프레쉬 방법 |
| US9047978B2 (en) | 2013-08-26 | 2015-06-02 | Micron Technology, Inc. | Apparatuses and methods for selective row refreshes |
| JP5931236B1 (ja) * | 2015-02-05 | 2016-06-08 | 力晶科技股▲ふん▼有限公司 | 半導体装置の制御回路及び方法、並びに半導体装置 |
| US20170110178A1 (en) * | 2015-09-17 | 2017-04-20 | Intel Corporation | Hybrid refresh with hidden refreshes and external refreshes |
| US9715919B1 (en) | 2016-06-21 | 2017-07-25 | Micron Technology, Inc. | Array data bit inversion |
| KR102550685B1 (ko) | 2016-07-25 | 2023-07-04 | 에스케이하이닉스 주식회사 | 반도체장치 |
| KR102600320B1 (ko) * | 2016-09-26 | 2023-11-10 | 에스케이하이닉스 주식회사 | 리프레쉬 제어 장치 |
| US10394719B2 (en) * | 2017-01-25 | 2019-08-27 | Samsung Electronics Co., Ltd. | Refresh aware replacement policy for volatile memory cache |
| CN106875970B (zh) * | 2017-02-16 | 2021-06-01 | 上海兆芯集成电路有限公司 | 动态随机存取存储器控制器及其控制方法 |
| US10580475B2 (en) | 2018-01-22 | 2020-03-03 | Micron Technology, Inc. | Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device |
| US11152050B2 (en) | 2018-06-19 | 2021-10-19 | Micron Technology, Inc. | Apparatuses and methods for multiple row hammer refresh address sequences |
| US10622055B2 (en) * | 2018-08-21 | 2020-04-14 | Micron Technology, Inc. | Apparatus for supplying power supply voltage to semiconductor chip including volatile memory cell |
| US10685696B2 (en) | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
| WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
| US10957377B2 (en) | 2018-12-26 | 2021-03-23 | Micron Technology, Inc. | Apparatuses and methods for distributed targeted refresh operations |
| US10770127B2 (en) | 2019-02-06 | 2020-09-08 | Micron Technology, Inc. | Apparatuses and methods for managing row access counts |
| US11043254B2 (en) | 2019-03-19 | 2021-06-22 | Micron Technology, Inc. | Semiconductor device having cam that stores address signals |
| US11264096B2 (en) | 2019-05-14 | 2022-03-01 | Micron Technology, Inc. | Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits |
| US11158364B2 (en) | 2019-05-31 | 2021-10-26 | Micron Technology, Inc. | Apparatuses and methods for tracking victim rows |
| US11158373B2 (en) | 2019-06-11 | 2021-10-26 | Micron Technology, Inc. | Apparatuses, systems, and methods for determining extremum numerical values |
| US11139015B2 (en) | 2019-07-01 | 2021-10-05 | Micron Technology, Inc. | Apparatuses and methods for monitoring word line accesses |
| KR102767632B1 (ko) * | 2019-07-01 | 2025-02-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 메모리 시스템 |
| US10832792B1 (en) | 2019-07-01 | 2020-11-10 | Micron Technology, Inc. | Apparatuses and methods for adjusting victim data |
| US11386946B2 (en) | 2019-07-16 | 2022-07-12 | Micron Technology, Inc. | Apparatuses and methods for tracking row accesses |
| US10943636B1 (en) | 2019-08-20 | 2021-03-09 | Micron Technology, Inc. | Apparatuses and methods for analog row access tracking |
| US10964378B2 (en) | 2019-08-22 | 2021-03-30 | Micron Technology, Inc. | Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation |
| US11200942B2 (en) | 2019-08-23 | 2021-12-14 | Micron Technology, Inc. | Apparatuses and methods for lossy row access counting |
| US11302374B2 (en) * | 2019-08-23 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic refresh allocation |
| US11315618B2 (en) * | 2019-09-04 | 2022-04-26 | Winbond Electronics Corp. | Memory storage device and operation method thereof |
| US11222682B1 (en) | 2020-08-31 | 2022-01-11 | Micron Technology, Inc. | Apparatuses and methods for providing refresh addresses |
| CN114649044B (zh) * | 2020-12-21 | 2024-07-19 | 长鑫存储技术有限公司 | 自动刷新次数测试方法及装置 |
| US11462291B2 (en) | 2020-11-23 | 2022-10-04 | Micron Technology, Inc. | Apparatuses and methods for tracking word line accesses |
| US11482275B2 (en) | 2021-01-20 | 2022-10-25 | Micron Technology, Inc. | Apparatuses and methods for dynamically allocated aggressor detection |
| US11600314B2 (en) | 2021-03-15 | 2023-03-07 | Micron Technology, Inc. | Apparatuses and methods for sketch circuits for refresh binning |
| US11579797B2 (en) * | 2021-04-29 | 2023-02-14 | Micron Technology, Inc. | Memory sub-system refresh |
| CN115910140B (zh) * | 2021-08-09 | 2024-07-19 | 长鑫存储技术有限公司 | 刷新计数器电路、刷新计数方法及半导体存储 |
| US11869570B2 (en) * | 2021-08-09 | 2024-01-09 | Changxin Memory Technologies, Inc. | Refresh counter circuit, refresh counting method and semiconductor memory |
| US11664063B2 (en) | 2021-08-12 | 2023-05-30 | Micron Technology, Inc. | Apparatuses and methods for countering memory attacks |
| CN115995246B (zh) * | 2021-10-18 | 2025-07-25 | 长鑫存储技术有限公司 | 刷新电路、刷新方法及半导体存储器 |
| US11688451B2 (en) | 2021-11-29 | 2023-06-27 | Micron Technology, Inc. | Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking |
| US12165687B2 (en) | 2021-12-29 | 2024-12-10 | Micron Technology, Inc. | Apparatuses and methods for row hammer counter mat |
| US12125514B2 (en) | 2022-04-28 | 2024-10-22 | Micron Technology, Inc. | Apparatuses and methods for access based refresh operations |
| US12112787B2 (en) | 2022-04-28 | 2024-10-08 | Micron Technology, Inc. | Apparatuses and methods for access based targeted refresh operations |
| CN117198357A (zh) * | 2022-05-30 | 2023-12-08 | 长鑫存储技术有限公司 | 一种刷新地址产生电路 |
| CN117636942B (zh) * | 2024-01-26 | 2024-05-03 | 长鑫存储技术(西安)有限公司 | 刷新控制结构、刷新控制方法及存储器 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4106408A (en) * | 1975-08-13 | 1978-08-15 | Addressograph Multigraph Corporation | Duplicator cylinder construction |
| IT1041882B (it) * | 1975-08-20 | 1980-01-10 | Honeywell Inf Systems | Memoria dinamica a semiconduttori e relativo sistema di recarica |
| JPH05151772A (ja) * | 1991-11-29 | 1993-06-18 | Nec Corp | リフレツシユ制御回路 |
| KR100372245B1 (ko) * | 1995-08-24 | 2004-02-25 | 삼성전자주식회사 | 워드라인순차제어반도체메모리장치 |
| US5627791A (en) | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
| US6104658A (en) * | 1996-08-08 | 2000-08-15 | Neomagic Corporation | Distributed DRAM refreshing |
| JPH10247384A (ja) * | 1997-03-03 | 1998-09-14 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
| JP2000163956A (ja) | 1998-11-24 | 2000-06-16 | Sharp Corp | 半導体記憶装置 |
| JP2004288226A (ja) * | 2001-03-30 | 2004-10-14 | Internatl Business Mach Corp <Ibm> | Ｄｒａｍ及びｄｒａｍのリフレッシュ方法 |
| US6529433B2 (en) * | 2001-04-03 | 2003-03-04 | Hynix Semiconductor, Inc. | Refresh mechanism in dynamic memories |
| KR100429872B1 (ko) * | 2001-06-27 | 2004-05-04 | 삼성전자주식회사 | 반도체 메모리 장치의 이용 효율을 높이는 메모리 시스템및 상기 반도체 메모리 장치의 리프레쉬 방법 |
| JP4768163B2 (ja) | 2001-08-03 | 2011-09-07 | 富士通セミコンダクター株式会社 | 半導体メモリ |
| TW533413B (en) | 2001-10-11 | 2003-05-21 | Cascade Semiconductor Corp | Asynchronous hidden refresh of semiconductor memory |
| US6625077B2 (en) * | 2001-10-11 | 2003-09-23 | Cascade Semiconductor Corporation | Asynchronous hidden refresh of semiconductor memory |
| KR100465597B1 (ko) | 2001-12-07 | 2005-01-13 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 리프레쉬장치 및 그것의 리프레쉬방법 |
| CN2711801Y (zh) * | 2003-12-19 | 2005-07-20 | 中国科学院长春光学精密机械与物理研究所 | 一种刷新时序信号发生器 |
| US6967885B2 (en) * | 2004-01-15 | 2005-11-22 | International Business Machines Corporation | Concurrent refresh mode with distributed row address counters in an embedded DRAM |
| KR100745074B1 (ko) * | 2005-12-28 | 2007-08-01 | 주식회사 하이닉스반도체 | 반도체 장치 |
| KR100803352B1 (ko) * | 2006-06-12 | 2008-02-14 | 주식회사 하이닉스반도체 | 반도체 메모리의 리프레쉬 제어장치 및 방법 |
-
2006
- 2006-03-30 JP JP2006093827A patent/JP4912718B2/ja not_active Expired - Fee Related
- 2006-06-12 EP EP06115323A patent/EP1840900B1/en not_active Not-in-force
- 2006-06-12 TW TW095120834A patent/TWI312515B/zh not_active IP Right Cessation
- 2006-06-12 DE DE602006006545T patent/DE602006006545D1/de active Active
- 2006-06-12 US US11/450,472 patent/US7630268B2/en not_active Expired - Fee Related
- 2006-07-05 KR KR1020060062920A patent/KR100868713B1/ko not_active Expired - Fee Related
- 2006-07-06 CN CN2006100985634A patent/CN101047025B/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP1840900B1 (en) | 2009-04-29 |
| JP4912718B2 (ja) | 2012-04-11 |
| CN101047025B (zh) | 2010-04-21 |
| TWI312515B (en) | 2009-07-21 |
| KR20070098390A (ko) | 2007-10-05 |
| EP1840900A1 (en) | 2007-10-03 |
| TW200737190A (en) | 2007-10-01 |
| KR100868713B1 (ko) | 2008-11-13 |
| US20070230264A1 (en) | 2007-10-04 |
| CN101047025A (zh) | 2007-10-03 |
| US7630268B2 (en) | 2009-12-08 |
| JP2007272938A (ja) | 2007-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE602006006545D1 (de) | Dynamischer Halbleiterspeicher mit Reduzierung der Häufigkeit von Aktualisierungsbefehlsanfragen und Aktualisierungssteuerverfahren dafür | |
| DE60326534D1 (de) | Regelalgorithmus zur dynamischen Inversion mit Randbedingungen | |
| DE602006019010D1 (de) | Speicheranordnung und auffrisch-justierverfahren | |
| DE602007000394D1 (de) | Halbleiterspeicher mit internem und externem Refresh | |
| NL1029182A1 (nl) | Werkwijzen en toestellen voor het ontwerp van visuele applicaties. | |
| DE602006011179D1 (de) | Fahrzeug mit steuervorrichtung und fahrzeugsteuerverfahren | |
| EP1754814A4 (en) | FRAME KNITTED WITH POLYURETHANE ELASTOMERIC FIBERS AND PROCESS FOR PRODUCING THE SAME | |
| EP1726795A4 (en) | STRUCTURAL BODY OF BEES AND APPARATUS FOR EXHAUST GAS PURIFICATION | |
| EP2225507A4 (en) | REFRIGERATOR AND CONTROL METHOD THEREOF | |
| ATE539064T1 (de) | Heterozyklische inhibitoren von mek und verwendungsverfahren damit | |
| EP1819297A4 (en) | ULTRAVIOLET DRY GEL AND PROCESS FOR PRODUCING THE SAME | |
| DE602006019033D1 (de) | Fahrendes Objekt und dessen Steuerungsverfahren | |
| DE602004008739D1 (de) | Speichersystem und dazugehöriges Steuerverfahren | |
| DE602007012296D1 (de) | Fahrgetriebe und steuerungsverfahren dafür | |
| EP1888081A4 (en) | COMPOSITIONS CONTAINING POLYUNSATURATED FATTY ACIDS AND METHODS OF USE | |
| DE602007010852D1 (de) | Element mit magnetoresistivem Effekt und Herstellungsverfahren dafür | |
| DE602006010481D1 (de) | Speichersteuerung und Steuerverfahren dafür | |
| DE602004002280D1 (de) | Halbleiterspeicher mit Refresh- und Redundanzschaltungen | |
| DE602006011292D1 (de) | Cache-speichersystem und steuerverfahren dafür | |
| DE112007001839A5 (de) | Integrierte Schaltungsanordnung und Verwendung von Zuleitungen | |
| DE602005004508D1 (de) | Speichersystem und Speichersteuerverfahren | |
| DE602008002043D1 (de) | Speicherkontrollvorrichtung und Speicherkontrollverfahren | |
| DE602006019083D1 (de) | Speichervorrichtung mit integrierter schaltung, syeihen und spalten | |
| DE602004009443D1 (de) | Kombination von eigen- und formanisotropie zwecks reduzierter umschaltfeldfluktuationen | |
| DE602004010928D1 (de) | Speichersystem und Computersystem |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
|
| 8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |