DE602006003201D1 - Simultane kernprüfung in integrierten schaltungen mit mehreren kernen - Google Patents

Simultane kernprüfung in integrierten schaltungen mit mehreren kernen

Info

Publication number
DE602006003201D1
DE602006003201D1 DE602006003201T DE602006003201T DE602006003201D1 DE 602006003201 D1 DE602006003201 D1 DE 602006003201D1 DE 602006003201 T DE602006003201 T DE 602006003201T DE 602006003201 T DE602006003201 T DE 602006003201T DE 602006003201 D1 DE602006003201 D1 DE 602006003201D1
Authority
DE
Germany
Prior art keywords
integrated circuits
multiple core
simultaneous check
simultaneous
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006003201T
Other languages
English (en)
Inventor
Ting-Yu Kuo
Dwight K Elvey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE602006003201D1 publication Critical patent/DE602006003201D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE602006003201T 2005-03-22 2006-03-21 Simultane kernprüfung in integrierten schaltungen mit mehreren kernen Active DE602006003201D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/086,924 US7685487B1 (en) 2005-03-22 2005-03-22 Simultaneous core testing in multi-core integrated circuits
PCT/US2006/010233 WO2006102325A1 (en) 2005-03-22 2006-03-21 Simultaneous core testing in multi-core integrated circuits

Publications (1)

Publication Number Publication Date
DE602006003201D1 true DE602006003201D1 (de) 2008-11-27

Family

ID=36608659

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006003201T Active DE602006003201D1 (de) 2005-03-22 2006-03-21 Simultane kernprüfung in integrierten schaltungen mit mehreren kernen

Country Status (8)

Country Link
US (1) US7685487B1 (de)
EP (1) EP1872146B1 (de)
JP (1) JP5723515B2 (de)
KR (1) KR101256976B1 (de)
CN (1) CN101147077B (de)
DE (1) DE602006003201D1 (de)
TW (1) TWI407122B (de)
WO (1) WO2006102325A1 (de)

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US8694845B2 (en) * 2010-04-25 2014-04-08 Ssu-Pin Ma Methods and systems for testing electronic circuits
US9317351B2 (en) * 2010-09-07 2016-04-19 Advantest Corporation System, methods and apparatus using virtual appliances in a semiconductor test environment
US9336105B2 (en) 2010-09-30 2016-05-10 International Business Machines Corporation Evaluation of multiple input signature register results
JP5900061B2 (ja) * 2012-03-19 2016-04-06 富士通株式会社 試験方法、試験装置及びプログラム
US9262292B2 (en) * 2012-06-11 2016-02-16 New York University Test access system, method and computer-accessible medium for chips with spare identical cores
KR101457557B1 (ko) 2013-01-18 2014-11-04 연세대학교 산학협력단 멀티코어 장치, 테스트 장치 및 고장 진단 방법
US9274911B2 (en) 2013-02-21 2016-03-01 Advantest Corporation Using shared pins in a concurrent test execution environment
US9274172B2 (en) 2013-10-17 2016-03-01 International Business Machines Corporation Selective test pattern processor
US9355061B2 (en) 2014-01-28 2016-05-31 Arm Limited Data processing apparatus and method for performing scan operations
JP6328974B2 (ja) * 2014-03-28 2018-05-23 株式会社メガチップス 半導体装置及び半導体装置の設計手法
TWI530702B (zh) * 2014-12-17 2016-04-21 力晶科技股份有限公司 晶片可靠度的測試板及其測試系統
US20170184665A1 (en) * 2015-12-28 2017-06-29 Qualcomm Incorporated Dynamically configurable shared scan clock channel architecture
KR20180113113A (ko) * 2017-04-05 2018-10-15 에스케이하이닉스 주식회사 테스트 패드를 구비한 반도체 집적 회로 장치
TWI655548B (zh) * 2017-10-13 2019-04-01 技嘉科技股份有限公司 介面優先排程及解決衝突之控制電路及介面優先排程及解決衝突之操作方法
US10352998B2 (en) * 2017-10-17 2019-07-16 Microchip Technology Incorporated Multi-processor core device with MBIST
US10628275B2 (en) * 2018-03-07 2020-04-21 Nxp B.V. Runtime software-based self-test with mutual inter-core checking
WO2020068980A1 (en) * 2018-09-28 2020-04-02 Celerint, Llc Method for in situ functionality testing of switches and contacts in semiconductor interface hardware
US11067623B2 (en) * 2019-05-19 2021-07-20 Test Research, Inc. Test system and method of operating the same
US11048603B2 (en) 2019-05-22 2021-06-29 International Business Machines Corporation Critical path failure analysis using hardware instruction injection
JP7150676B2 (ja) 2019-09-02 2022-10-11 株式会社東芝 半導体集積回路及びそのテスト方法
US11342914B2 (en) * 2020-06-19 2022-05-24 Juniper Networks, Inc. Integrated circuit having state machine-driven flops in wrapper chains for device testing
CN111766505B (zh) * 2020-06-30 2023-04-25 山东云海国创云计算装备产业创新中心有限公司 一种集成电路的扫描测试装置
TWI760157B (zh) * 2021-03-24 2022-04-01 德律科技股份有限公司 多核並行測試單一待測物的系統及方法
CN113203940B (zh) * 2021-04-29 2023-06-20 桂林电子科技大学 3D NoC测试规划中的并行测试方法
CN116400202B (zh) * 2023-06-07 2023-09-01 中国汽车技术研究中心有限公司 一种芯片逻辑功能交叉验证测试方法

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JP2003098225A (ja) * 2001-09-25 2003-04-03 Toshiba Corp 半導体集積回路
JP2003223798A (ja) * 2002-01-25 2003-08-08 Mitsubishi Electric Corp テスト容易化回路
KR100448706B1 (ko) * 2002-07-23 2004-09-13 삼성전자주식회사 단일 칩 시스템 및 이 시스템의 테스트/디버그 방법
JP2004347537A (ja) * 2003-05-23 2004-12-09 Matsushita Electric Ind Co Ltd 半導体集積回路
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Also Published As

Publication number Publication date
JP5723515B2 (ja) 2015-05-27
TW200643441A (en) 2006-12-16
WO2006102325A1 (en) 2006-09-28
CN101147077A (zh) 2008-03-19
EP1872146A1 (de) 2008-01-02
JP2008534928A (ja) 2008-08-28
KR20070121011A (ko) 2007-12-26
KR101256976B1 (ko) 2013-04-19
EP1872146B1 (de) 2008-10-15
CN101147077B (zh) 2010-09-29
TWI407122B (zh) 2013-09-01
US7685487B1 (en) 2010-03-23

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