DE602005020270D1 - Bitleitungs-implantat mit doppel-poly - Google Patents

Bitleitungs-implantat mit doppel-poly

Info

Publication number
DE602005020270D1
DE602005020270D1 DE602005020270T DE602005020270T DE602005020270D1 DE 602005020270 D1 DE602005020270 D1 DE 602005020270D1 DE 602005020270 T DE602005020270 T DE 602005020270T DE 602005020270 T DE602005020270 T DE 602005020270T DE 602005020270 D1 DE602005020270 D1 DE 602005020270D1
Authority
DE
Germany
Prior art keywords
implant
piping
bit
double poly
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005020270T
Other languages
English (en)
Inventor
Weidon Qian
Mark T Ramsbey
Jean Yee-Mei Yang
Sameer Haddad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Publication of DE602005020270D1 publication Critical patent/DE602005020270D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
DE602005020270T 2004-05-11 2005-02-11 Bitleitungs-implantat mit doppel-poly Active DE602005020270D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/843,289 US6989320B2 (en) 2004-05-11 2004-05-11 Bitline implant utilizing dual poly
PCT/US2005/004540 WO2005114734A1 (en) 2004-05-11 2005-02-11 Bitline implant utilizing dual poly

Publications (1)

Publication Number Publication Date
DE602005020270D1 true DE602005020270D1 (de) 2010-05-12

Family

ID=34960655

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005020270T Active DE602005020270D1 (de) 2004-05-11 2005-02-11 Bitleitungs-implantat mit doppel-poly

Country Status (8)

Country Link
US (1) US6989320B2 (de)
EP (1) EP1745511B1 (de)
JP (1) JP4922926B2 (de)
KR (1) KR101136140B1 (de)
CN (1) CN100479169C (de)
DE (1) DE602005020270D1 (de)
TW (1) TWI381457B (de)
WO (1) WO2005114734A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7087532B2 (en) * 2004-09-30 2006-08-08 International Business Machines Corporation Formation of controlled sublithographic structures
KR100669089B1 (ko) * 2005-07-11 2007-01-16 삼성전자주식회사 게이트 구조물, 이를 갖는 소노스 타입의 비휘발성 메모리장치 및 그 제조 방법
KR100788371B1 (ko) * 2006-08-02 2008-01-02 동부일렉트로닉스 주식회사 플래시 메모리 소자 제조 방법
US20080096357A1 (en) * 2006-10-20 2008-04-24 Spansion Llc Method for manufacturing a memory device
US7888218B2 (en) * 2006-12-20 2011-02-15 Spansion Llc Using thick spacer for bitline implant then remove
US8012830B2 (en) 2007-08-08 2011-09-06 Spansion Llc ORO and ORPRO with bit line trench to suppress transport program disturb
US7829936B2 (en) * 2007-10-17 2010-11-09 Spansion Llc Split charge storage node inner spacer process
JP5308024B2 (ja) * 2007-12-28 2013-10-09 スパンション エルエルシー 半導体装置およびその製造方法
CN101621033B (zh) * 2008-07-04 2011-06-15 中芯国际集成电路制造(上海)有限公司 刻蚀闪存中介电存储层的方法
JP5405066B2 (ja) * 2008-07-28 2014-02-05 スパンション エルエルシー 半導体装置の製造方法
CN101673735B (zh) * 2008-09-12 2011-11-16 台湾积体电路制造股份有限公司 默认多晶硅间距设计规则下的混合多晶硅间距单元设计结构及系统
US9556094B2 (en) * 2012-12-26 2017-01-31 Cheil Industries, Inc. Monomer, hardmask composition including monomer, and method for forming pattern by using hardmask composition
KR101566531B1 (ko) * 2012-12-27 2015-11-05 제일모직 주식회사 하드마스크 조성물용 모노머, 상기 모노머를 포함하는 하드마스크 조성물 및 상기 하드마스크 조성물을 사용하는 패턴형성방법
US8916432B1 (en) * 2014-01-21 2014-12-23 Cypress Semiconductor Corporation Methods to integrate SONOS into CMOS flow
JP2019102520A (ja) * 2017-11-29 2019-06-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (27)

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US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
JP2630278B2 (ja) * 1994-10-26 1997-07-16 日本電気株式会社 不揮発性半導体記憶装置及びその製造方法
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6271095B1 (en) 1999-02-22 2001-08-07 Advanced Micro Devices, Inc. Locally confined deep pocket process for ULSI mosfets
US6248635B1 (en) 1999-10-25 2001-06-19 Advanced Micro Devices, Inc. Process for fabricating a bit-line in a monos device using a dual layer hard mask
US6410388B1 (en) 2000-02-15 2002-06-25 Advanced Micro Devices, Inc. Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device
JP3573691B2 (ja) * 2000-07-03 2004-10-06 シャープ株式会社 不揮発性半導体記憶装置およびその製造方法
US6573140B1 (en) 2000-08-29 2003-06-03 Advanced Micro Devices, Inc. Process for making a dual bit memory device with isolated polysilicon floating gates
US6383952B1 (en) 2001-02-28 2002-05-07 Advanced Micro Devices, Inc. RELACS process to double the frequency or pitch of small feature formation
US6456533B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Higher program VT and faster programming rates based on improved erase methods
DE10110150A1 (de) * 2001-03-02 2002-09-19 Infineon Technologies Ag Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
JP2002261174A (ja) * 2001-03-02 2002-09-13 Sony Corp 不揮発性半導体記憶装置の製造方法
US6465303B1 (en) * 2001-06-20 2002-10-15 Advanced Micro Devices, Inc. Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory
US6436768B1 (en) 2001-06-27 2002-08-20 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices
US6762092B2 (en) 2001-08-08 2004-07-13 Sandisk Corporation Scalable self-aligned dual floating gate memory cell array and methods of forming the array
US6440797B1 (en) 2001-09-28 2002-08-27 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory
US6566194B1 (en) 2001-10-01 2003-05-20 Advanced Micro Devices, Inc. Salicided gate for virtual ground arrays
US6630384B1 (en) 2001-10-05 2003-10-07 Advanced Micro Devices, Inc. Method of fabricating double densed core gates in sonos flash memory
US6925007B2 (en) 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
TW510048B (en) 2001-11-16 2002-11-11 Macronix Int Co Ltd Manufacturing method of non-volatile memory
US6653190B1 (en) 2001-12-15 2003-11-25 Advanced Micro Devices, Inc. Flash memory with controlled wordline width
US6620717B1 (en) 2002-03-14 2003-09-16 Advanced Micro Devices, Inc. Memory with disposable ARC for wordline formation
US6479348B1 (en) * 2002-03-27 2002-11-12 Advanced Micro Devices, Inc. Method of making memory wordline hard mask extension
US6617215B1 (en) 2002-03-27 2003-09-09 Advanced Micro Devices, Inc. Memory wordline hard mask
KR100466197B1 (ko) * 2002-07-18 2005-01-13 주식회사 하이닉스반도체 플래시 메모리 셀 및 그 제조방법
US6872609B1 (en) * 2004-01-12 2005-03-29 Advanced Micro Devices, Inc. Narrow bitline using Safier for mirrorbit
US6958272B2 (en) * 2004-01-12 2005-10-25 Advanced Micro Devices, Inc. Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Also Published As

Publication number Publication date
KR101136140B1 (ko) 2012-04-17
EP1745511B1 (de) 2010-03-31
US20050255651A1 (en) 2005-11-17
KR20070017552A (ko) 2007-02-12
CN1954434A (zh) 2007-04-25
US6989320B2 (en) 2006-01-24
EP1745511A1 (de) 2007-01-24
TWI381457B (zh) 2013-01-01
JP4922926B2 (ja) 2012-04-25
WO2005114734A1 (en) 2005-12-01
TW200614388A (en) 2006-05-01
JP2007537592A (ja) 2007-12-20
CN100479169C (zh) 2009-04-15

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