DE60329574D1 - Vorausladungsmechanismus mit Speicherabsicht - Google Patents

Vorausladungsmechanismus mit Speicherabsicht

Info

Publication number
DE60329574D1
DE60329574D1 DE60329574T DE60329574T DE60329574D1 DE 60329574 D1 DE60329574 D1 DE 60329574D1 DE 60329574 T DE60329574 T DE 60329574T DE 60329574 T DE60329574 T DE 60329574T DE 60329574 D1 DE60329574 D1 DE 60329574D1
Authority
DE
Germany
Prior art keywords
intent
storage
loading mechanism
loading
storage intent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60329574T
Other languages
English (en)
Inventor
Rodney E Hooker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IP First LLC
Original Assignee
IP First LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IP First LLC filed Critical IP First LLC
Application granted granted Critical
Publication of DE60329574D1 publication Critical patent/DE60329574D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE60329574T 2003-02-11 2003-06-04 Vorausladungsmechanismus mit Speicherabsicht Expired - Lifetime DE60329574D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/364,911 US7080210B2 (en) 2002-02-12 2003-02-11 Microprocessor apparatus and method for exclusive prefetch of a cache line from memory

Publications (1)

Publication Number Publication Date
DE60329574D1 true DE60329574D1 (de) 2009-11-19

Family

ID=32681697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60329574T Expired - Lifetime DE60329574D1 (de) 2003-02-11 2003-06-04 Vorausladungsmechanismus mit Speicherabsicht

Country Status (5)

Country Link
US (1) US7080210B2 (de)
EP (1) EP1447745B1 (de)
CN (1) CN1266588C (de)
DE (1) DE60329574D1 (de)
TW (1) TWI220196B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095640A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Methods and apparatus for efficient communication between caches in hierarchical caching design
US10656945B2 (en) 2012-06-15 2020-05-19 International Business Machines Corporation Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction
US9170955B2 (en) * 2012-11-27 2015-10-27 Intel Corporation Providing extended cache replacement state information
US9158702B2 (en) 2012-12-28 2015-10-13 Intel Corporation Apparatus and method for implementing a scratchpad memory using priority hint
JP6055456B2 (ja) * 2014-10-31 2016-12-27 インテル・コーポレーション 階層的キャッシュ設計におけるキャッシュ間の効率的通信のための方法および装置
US10509726B2 (en) * 2015-12-20 2019-12-17 Intel Corporation Instructions and logic for load-indices-and-prefetch-scatters operations
US10572263B2 (en) * 2016-03-31 2020-02-25 International Business Machines Corporation Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution
CN109597776B (zh) * 2017-09-30 2020-12-08 华为技术有限公司 一种数据操作方法、内存控制器以及多处理器系统
CN113377704B (zh) * 2021-06-11 2022-04-12 上海壁仞智能科技有限公司 人工智能芯片以及数据操作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959777A (en) * 1987-07-27 1990-09-25 Motorola Computer X Write-shared cache circuit for multiprocessor system
CA2051209C (en) 1990-11-30 1996-05-07 Pradeep S. Sindhu Consistency protocols for shared memory multiprocessors
JP2500101B2 (ja) * 1992-12-18 1996-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 共用変数の値を更新する方法
US5903911A (en) * 1993-06-22 1999-05-11 Dell Usa, L.P. Cache-based computer system employing memory control circuit and method for write allocation and data prefetch
US5892970A (en) * 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
EP0825538A1 (de) 1996-08-16 1998-02-25 Lsi Logic Corporation Cachespeichersystem
US5966734A (en) * 1996-10-18 1999-10-12 Samsung Electronics Co., Ltd. Resizable and relocatable memory scratch pad as a cache slice
US6018763A (en) * 1997-05-28 2000-01-25 3Com Corporation High performance shared memory for a bridge router supporting cache coherency
US5944815A (en) * 1998-01-12 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access
US6014735A (en) 1998-03-31 2000-01-11 Intel Corporation Instruction set extension using prefixes
US6088789A (en) * 1998-05-13 2000-07-11 Advanced Micro Devices, Inc. Prefetch instruction specifying destination functional unit and read/write access mode
US6253306B1 (en) * 1998-07-29 2001-06-26 Advanced Micro Devices, Inc. Prefetch instruction mechanism for processor
US6289420B1 (en) * 1999-05-06 2001-09-11 Sun Microsystems, Inc. System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem
US6266744B1 (en) * 1999-05-18 2001-07-24 Advanced Micro Devices, Inc. Store to load forwarding using a dependency link file
US6470444B1 (en) * 1999-06-16 2002-10-22 Intel Corporation Method and apparatus for dividing a store operation into pre-fetch and store micro-operations
US6557084B2 (en) * 1999-07-13 2003-04-29 International Business Machines Corporation Apparatus and method to improve performance of reads from and writes to shared memory locations
US6460132B1 (en) * 1999-08-31 2002-10-01 Advanced Micro Devices, Inc. Massively parallel instruction predecoding
JP2001222466A (ja) * 2000-02-10 2001-08-17 Nec Corp マルチプロセッサ・システムと共有メモリ制御システム及び方法並びに記録媒体
US6751710B2 (en) * 2000-06-10 2004-06-15 Hewlett-Packard Development Company, L.P. Scalable multiprocessor system and cache coherence method
US6845008B2 (en) * 2001-03-30 2005-01-18 Intel Corporation Docking station to cool a notebook computer
US6915415B2 (en) * 2002-01-07 2005-07-05 International Business Machines Corporation Method and apparatus for mapping software prefetch instructions to hardware prefetch logic
US7380103B2 (en) * 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US6832296B2 (en) 2002-04-09 2004-12-14 Ip-First, Llc Microprocessor with repeat prefetch instruction

Also Published As

Publication number Publication date
EP1447745B1 (de) 2009-10-07
US7080210B2 (en) 2006-07-18
US20030177315A1 (en) 2003-09-18
CN1514349A (zh) 2004-07-21
EP1447745A3 (de) 2004-11-10
TW200415472A (en) 2004-08-16
EP1447745A2 (de) 2004-08-18
CN1266588C (zh) 2006-07-26
TWI220196B (en) 2004-08-11

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