DE602004019545D1 - Empfängerschaltung, schnittstellenschaltung und elektronsiche einrichtung - Google Patents

Empfängerschaltung, schnittstellenschaltung und elektronsiche einrichtung

Info

Publication number
DE602004019545D1
DE602004019545D1 DE602004019545T DE602004019545T DE602004019545D1 DE 602004019545 D1 DE602004019545 D1 DE 602004019545D1 DE 602004019545 T DE602004019545 T DE 602004019545T DE 602004019545 T DE602004019545 T DE 602004019545T DE 602004019545 D1 DE602004019545 D1 DE 602004019545D1
Authority
DE
Germany
Prior art keywords
interface
electronic equipment
receiver
interface circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004019545T
Other languages
English (en)
Inventor
Yukinari Shibata
Nobuyuki Saito
Tomonaga Hasegawa
Takuya Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE602004019545D1 publication Critical patent/DE602004019545D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Circuits Of Receivers In General (AREA)
DE602004019545T 2003-09-05 2004-09-06 Empfängerschaltung, schnittstellenschaltung und elektronsiche einrichtung Active DE602004019545D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003314055 2003-09-05
JP2004014412 2004-01-22
JP2004065938A JP3891185B2 (ja) 2003-09-05 2004-03-09 レシーバ回路、インターフェース回路、及び電子機器
PCT/JP2004/012933 WO2005025066A1 (ja) 2003-09-05 2004-09-06 レシーバ回路、インターフェース回路、及び電子機器

Publications (1)

Publication Number Publication Date
DE602004019545D1 true DE602004019545D1 (de) 2009-04-02

Family

ID=34279563

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004019545T Active DE602004019545D1 (de) 2003-09-05 2004-09-06 Empfängerschaltung, schnittstellenschaltung und elektronsiche einrichtung

Country Status (7)

Country Link
US (1) US7535257B2 (de)
EP (1) EP1662657B1 (de)
JP (1) JP3891185B2 (de)
KR (1) KR100647185B1 (de)
CN (1) CN100337403C (de)
DE (1) DE602004019545D1 (de)
WO (1) WO2005025066A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3807406B2 (ja) * 2003-09-05 2006-08-09 セイコーエプソン株式会社 データ転送制御装置及び電子機器
JP3807407B2 (ja) * 2003-09-05 2006-08-09 セイコーエプソン株式会社 トランスミッタ回路、レシーバ回路、インターフェース回路、及び電子機器
KR100768854B1 (ko) * 2005-09-29 2007-10-22 엘지전자 주식회사 저전력 기능을 구비한 이동단말기 및 그의 구동 방법
US7710188B1 (en) * 2006-01-13 2010-05-04 Marvell International Ltd. Low-noise, temperature-insensitive, voltage or current input, analog front end architecture
JP2008005114A (ja) * 2006-06-21 2008-01-10 Seiko Epson Corp 受信装置および送受信システム
JP4775308B2 (ja) * 2007-04-25 2011-09-21 株式会社日立製作所 回路ブロック間送受信回路を持つ半導体装置
US7605635B2 (en) * 2007-05-24 2009-10-20 National Semiconductor Corporation Threshold control circuitry for multiple current signal receivers
WO2008149480A1 (ja) 2007-06-05 2008-12-11 Panasonic Corporation 受信回路及びデータ伝送システム
JP4404122B2 (ja) * 2007-09-07 2010-01-27 セイコーエプソン株式会社 高速シリアルインターフェース回路及び電子機器
JP5645272B2 (ja) * 2009-11-13 2014-12-24 パナソニックＩｐマネジメント株式会社 ドライバ回路、レシーバ回路及びそれらを含む通信システムの制御方法
US8441299B2 (en) * 2010-01-28 2013-05-14 Peregrine Semiconductor Corporation Dual path level shifter
CN102213999B (zh) * 2010-04-12 2013-05-01 辉芒微电子（深圳）有限公司 单线接口电路
ES2649341T3 (es) * 2011-12-14 2018-01-11 Intel Corporation Unidad lógica secuencial de múltiples suministros de energía
US8885695B1 (en) * 2013-06-26 2014-11-11 Global Unichip Corporation Receiver circuit
JP6490339B2 (ja) * 2013-11-28 2019-03-27 ザインエレクトロニクス株式会社 送信装置，受信装置および送受信システム
KR102243310B1 (ko) 2014-08-19 2021-04-23 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
US9531352B1 (en) 2015-06-24 2016-12-27 Intel Corporation Latched comparator circuit
JP6766352B2 (ja) * 2015-12-15 2020-10-14 ブラザー工業株式会社 インタフェース回路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132968A (ja) 1992-10-20 1994-05-13 Sharp Corp 電源制御機能を備える通信装置
US5546021A (en) * 1994-02-14 1996-08-13 Motorola, Inc. 3-state bicmos output buffer having power down capability
JPH07264042A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd 高速インタフェース回路
JPH08162942A (ja) 1994-11-29 1996-06-21 Mitsubishi Electric Corp 出力回路、入力回路、およびこれらを用いた入出力インタフェースシステム
JP3835884B2 (ja) * 1997-04-30 2006-10-18 株式会社 沖マイクロデザイン 半導体集積回路の入力回路
US6188271B1 (en) * 1998-07-13 2001-02-13 Minhui Wang Fail safe bias system for a tri-state bus
US6317839B1 (en) * 1999-01-19 2001-11-13 International Business Machines Corporation Method of and apparatus for controlling supply of power to a peripheral device in a computer system
US6320406B1 (en) * 1999-10-04 2001-11-20 Texas Instruments Incorporated Methods and apparatus for a terminated fail-safe circuit
DE19959982C2 (de) * 1999-12-13 2001-10-04 Siemens Ag Verfahren und Anordnung zur Überwachung der Datenübertragung mittels differentiellen Übertragungsverfahren mit Gleichspannungsanteil
JP2002314397A (ja) * 2001-04-17 2002-10-25 Seiko Epson Corp 差動信号出力回路
EP1304842B1 (de) * 2001-10-19 2008-05-14 Texas Instruments Incorporated Serielle Differenzialdatenstrecke mit automatischer Abschaltung
JP3671920B2 (ja) 2001-11-15 2005-07-13 セイコーエプソン株式会社 スキュー調整回路及びスキュー調整方法
US7200186B2 (en) * 2002-03-14 2007-04-03 Intel Corporation Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link
US7170949B2 (en) * 2002-03-14 2007-01-30 Intel Corporation Methods and apparatus for signaling on a differential link
US6593801B1 (en) * 2002-06-07 2003-07-15 Pericom Semiconductor Corp. Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines

Also Published As

Publication number Publication date
EP1662657A1 (de) 2006-05-31
EP1662657A4 (de) 2007-01-03
KR20060035590A (ko) 2006-04-26
JP2005236930A (ja) 2005-09-02
JP3891185B2 (ja) 2007-03-14
WO2005025066A1 (ja) 2005-03-17
CN1778046A (zh) 2006-05-24
CN100337403C (zh) 2007-09-12
US20050088218A1 (en) 2005-04-28
US7535257B2 (en) 2009-05-19
KR100647185B1 (ko) 2006-11-23
EP1662657B1 (de) 2009-02-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition