DE60132152D1 - Herstellungsverfahren von einem randlosen Kontakt auf Bitleitungskontaktstutzen mit einer Ätzstopschicht - Google Patents

Herstellungsverfahren von einem randlosen Kontakt auf Bitleitungskontaktstutzen mit einer Ätzstopschicht

Info

Publication number
DE60132152D1
DE60132152D1 DE60132152T DE60132152T DE60132152D1 DE 60132152 D1 DE60132152 D1 DE 60132152D1 DE 60132152 T DE60132152 T DE 60132152T DE 60132152 T DE60132152 T DE 60132152T DE 60132152 D1 DE60132152 D1 DE 60132152D1
Authority
DE
Germany
Prior art keywords
contact
producing
bit line
stop layer
etch stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60132152T
Other languages
English (en)
Other versions
DE60132152T2 (de
Inventor
Hong-Sik Jeong
Won-Suk Yang
Ki-Nam Ki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE60132152D1 publication Critical patent/DE60132152D1/de
Application granted granted Critical
Publication of DE60132152T2 publication Critical patent/DE60132152T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
DE60132152T 2000-10-30 2001-06-22 Herstellungsverfahren von einem randlosen Kontakt auf Bitleitungskontaktstutzen mit einer Ätzstopschicht Expired - Lifetime DE60132152T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/699,849 US6350649B1 (en) 2000-10-30 2000-10-30 Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof
US699849 2000-10-30

Publications (2)

Publication Number Publication Date
DE60132152D1 true DE60132152D1 (de) 2008-02-14
DE60132152T2 DE60132152T2 (de) 2008-12-11

Family

ID=24811177

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60132152T Expired - Lifetime DE60132152T2 (de) 2000-10-30 2001-06-22 Herstellungsverfahren von einem randlosen Kontakt auf Bitleitungskontaktstutzen mit einer Ätzstopschicht

Country Status (6)

Country Link
US (1) US6350649B1 (de)
EP (1) EP1202340B1 (de)
JP (1) JP4057800B2 (de)
KR (1) KR100416591B1 (de)
DE (1) DE60132152T2 (de)
TW (1) TW573340B (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6373740B1 (en) * 1999-07-30 2002-04-16 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6518671B1 (en) * 2000-10-30 2003-02-11 Samsung Electronics Co. Ltd. Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof
US6787906B1 (en) * 2000-10-30 2004-09-07 Samsung Electronics Co., Ltd. Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region
KR100382738B1 (ko) * 2001-04-09 2003-05-09 삼성전자주식회사 반도체 소자의 메탈 컨택 형성 방법
US7101770B2 (en) * 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections
US6846738B2 (en) * 2002-03-13 2005-01-25 Micron Technology, Inc. High permeability composite films to reduce noise in high speed interconnects
US7235457B2 (en) 2002-03-13 2007-06-26 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US6970053B2 (en) * 2003-05-22 2005-11-29 Micron Technology, Inc. Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
KR100520227B1 (ko) * 2003-12-26 2005-10-11 삼성전자주식회사 반도체 메모리장치의 제조방법 및 그에 따른 구조
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
KR100733460B1 (ko) * 2005-12-28 2007-06-29 주식회사 하이닉스반도체 반도체 소자의 메탈 콘택 형성 방법
KR100683492B1 (ko) * 2005-12-28 2007-02-15 주식회사 하이닉스반도체 반도체소자의 콘택식각 방법
KR100866701B1 (ko) * 2007-03-23 2008-11-04 주식회사 하이닉스반도체 반도체 소자의 제조 방법
JP5613388B2 (ja) * 2009-07-23 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置の製造方法
TWI463934B (zh) * 2012-10-03 2014-12-01 Macronix Int Co Ltd 積體電路及其製造方法
KR102264601B1 (ko) 2014-07-21 2021-06-14 삼성전자주식회사 자기 메모리 소자 및 이의 제조 방법
CN108735741B (zh) * 2017-04-13 2020-10-09 联华电子股份有限公司 存储器元件中的存储点接触结构与其制作方法
WO2021106757A1 (ja) 2019-11-28 2021-06-03 ソニー株式会社 レーザ素子、レーザ素子の製造方法、レーザ装置およびレーザ増幅素子

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966870A (en) 1988-04-14 1990-10-30 International Business Machines Corporation Method for making borderless contacts
US5612254A (en) 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5466636A (en) 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
US5708559A (en) * 1995-10-27 1998-01-13 International Business Machines Corporation Precision analog metal-metal capacitor
US5808335A (en) 1996-06-13 1998-09-15 Vanguard International Semiconductor Corporation Reduced mask DRAM process
KR100213209B1 (ko) * 1996-07-29 1999-08-02 윤종용 반도체장치의 제조방법
TW377495B (en) * 1996-10-04 1999-12-21 Hitachi Ltd Method of manufacturing semiconductor memory cells and the same apparatus
US5891799A (en) 1997-08-18 1999-04-06 Industrial Technology Research Institute Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
US6025259A (en) * 1998-07-02 2000-02-15 Advanced Micro Devices, Inc. Dual damascene process using high selectivity boundary layers
US6083824A (en) 1998-07-13 2000-07-04 Taiwan Semiconductor Manufacturing Company Borderless contact
US5918120A (en) 1998-07-24 1999-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
US5895239A (en) 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
US6156643A (en) * 1998-11-06 2000-12-05 Advanced Micro Devices, Inc. Method of forming a dual damascene trench and borderless via structure
US6022776A (en) 1999-04-07 2000-02-08 Worldwide Semiconductor Manufacturing Corporation Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads

Also Published As

Publication number Publication date
KR100416591B1 (ko) 2004-02-05
DE60132152T2 (de) 2008-12-11
JP4057800B2 (ja) 2008-03-05
EP1202340A3 (de) 2004-01-07
JP2002151588A (ja) 2002-05-24
EP1202340A2 (de) 2002-05-02
TW573340B (en) 2004-01-21
KR20020033484A (ko) 2002-05-07
US6350649B1 (en) 2002-02-26
EP1202340B1 (de) 2008-01-02

Similar Documents

Publication Publication Date Title
DE60132152D1 (de) Herstellungsverfahren von einem randlosen Kontakt auf Bitleitungskontaktstutzen mit einer Ätzstopschicht
DE60325603D1 (de) Gewinnungsverfahren einer unverseifbaren avocadofraktion mit einem höheren furanlipidengehalt
DE60045375D1 (de) Verfahren zur ätzung einer schicht mit niedriger dielektrizitätskonstante
DE50206750D1 (de) System mit einer werkzeugaufnahme
DE69941464D1 (de) Schnelles Ethernet mit einer Bitfolgefrequenz von 150 Mps
DE69802661D1 (de) Methode zum Umformen einer Substratoberfläche
DE60001776D1 (de) Einkapselungsverfahren einer halbleiteranordnung mit einem anisotropisch leitenden klebstoff
DE60130742D1 (de) Mustererkennung mit hierarchischen Netzen
DE69806861T2 (de) Hartes Werkzeug mit einer mehrschichtigen Beschichtung
DE69535970D1 (de) Elektrolumineszente Vorrichtung mit einer organischen elektrolumineszenten Schicht
DE60238957D1 (de) Verfahren zur Reduktion der Mustergröße auf einer Photoresistschicht
DE602004006592D1 (de) Mikroaktuator mit einer dielektrischen Mikroemulsion
DK0889331T3 (da) Fremgangsmåde til 3D-modellering af impedansen i et heterogent medium
NO20032293D0 (no) En forbindelsesstruktur samt fremgangsmåte for å tilvirke en forbindelsesstruktur
DE69903206D1 (de) Magnetische Speicheranordnungen mit einer Vielzahl magnetischer Tunnelverbindungen
DE60333708D1 (de) Reifen mit einer Lauffläche aus mehreren Schichten
DE60142209D1 (de) Steuerverfahren einer elektrischen Schaltung
DE69941284D1 (de) Umsetzung einer Datenrate
DE60044008D1 (de) Verfahren zur Herstellung einer Anzeigevorrichtung mit leitenden Oberflächen auf einer lichtmodulierenden Schicht
DE50311920D1 (de) System mit einer werkzeugaufnahme
GB0029315D0 (en) Method of increasing the conductivity of a transparent conductive layer
DE60231275D1 (de) Herstellungsverfahren einer Zündkerze
DE69928893D1 (de) Reifen mit einer Lauffläche die elektrisch leitenden Klammern enthält
DE60103398D1 (de) Mustererzeugungsverfahren unter verwendung einer inorganischer antireflexionsschicht
DE60216825D1 (de) Verfahren zum herstellen einer im wesentlichen transparenten elektrisch leitenden schichtanordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition