DE60028847D1 - Verfahren mit reduzierter Maskenzahl für die Herstellung von Mischsspannung-CMOS mit Hochleistung-Transistoren und -I/O Transistoren von hoher Zuverlässigkeit - Google Patents

Verfahren mit reduzierter Maskenzahl für die Herstellung von Mischsspannung-CMOS mit Hochleistung-Transistoren und -I/O Transistoren von hoher Zuverlässigkeit

Info

Publication number
DE60028847D1
DE60028847D1 DE60028847T DE60028847T DE60028847D1 DE 60028847 D1 DE60028847 D1 DE 60028847D1 DE 60028847 T DE60028847 T DE 60028847T DE 60028847 T DE60028847 T DE 60028847T DE 60028847 D1 DE60028847 D1 DE 60028847D1
Authority
DE
Germany
Prior art keywords
transistors
production
count process
voltage cmos
high performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60028847T
Other languages
English (en)
Other versions
DE60028847T2 (de
Inventor
Mark S Rodder
Mahalingam Nandakumar
Manoj Mehrotra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE60028847D1 publication Critical patent/DE60028847D1/de
Publication of DE60028847T2 publication Critical patent/DE60028847T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B7/00—Signalling systems according to more than one of groups G08B3/00 - G08B6/00; Personal calling systems according to more than one of groups G08B3/00 - G08B6/00
    • G08B7/06—Signalling systems according to more than one of groups G08B3/00 - G08B6/00; Personal calling systems according to more than one of groups G08B3/00 - G08B6/00 using electric transmission, e.g. involving audible and visible signalling through the use of sound and light sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J36/00—Parts, details or accessories of cooking-vessels
    • A47J36/32—Time-controlled igniting mechanisms or alarm devices
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B17/00—Fire alarms; Alarms responsive to explosion
    • G08B17/06—Electric actuation of the alarm, e.g. using a thermally-operated switch
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B21/00—Alarms responsive to a single specified undesired or abnormal condition and not otherwise provided for
    • G08B21/18—Status alarms
    • G08B21/182—Level alarms, e.g. alarms responsive to variables exceeding a threshold
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J2202/00—Devices having temperature indicating means

Landscapes

  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Food Science & Technology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE60028847T 1999-02-08 2000-02-08 Verfahren mit reduzierter Maskenzahl für die Herstellung von Mischsspannung-CMOS mit Hochleistung-Transistoren und -I/O Transistoren von hoher Zuverlässigkeit Expired - Lifetime DE60028847T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11897999P 1999-02-08 1999-02-08
US118979P 1999-02-08

Publications (2)

Publication Number Publication Date
DE60028847D1 true DE60028847D1 (de) 2006-08-03
DE60028847T2 DE60028847T2 (de) 2006-12-07

Family

ID=22381923

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60028847T Expired - Lifetime DE60028847T2 (de) 1999-02-08 2000-02-08 Verfahren mit reduzierter Maskenzahl für die Herstellung von Mischsspannung-CMOS mit Hochleistung-Transistoren und -I/O Transistoren von hoher Zuverlässigkeit

Country Status (6)

Country Link
US (1) US6258644B1 (de)
EP (1) EP1026738B1 (de)
JP (1) JP2000232167A (de)
KR (1) KR20000071335A (de)
DE (1) DE60028847T2 (de)
TW (1) TW459291B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166417A (en) * 1998-06-30 2000-12-26 Intel Corporation Complementary metal gates and a process for implementation
US6878968B1 (en) * 1999-05-10 2005-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2001127171A (ja) * 1999-10-26 2001-05-11 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
US6479339B2 (en) * 2000-10-10 2002-11-12 Texas Instruments Incorporated Use of a thin nitride spacer in a split gate embedded analog process
US6541819B2 (en) * 2001-05-24 2003-04-01 Agere Systems Inc. Semiconductor device having non-power enhanced and power enhanced metal oxide semiconductor devices and a method of manufacture therefor
JP4665141B2 (ja) * 2001-06-29 2011-04-06 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP5073136B2 (ja) * 2001-08-24 2012-11-14 ルネサスエレクトロニクス株式会社 半導体装置
KR100450666B1 (ko) * 2001-09-03 2004-10-01 삼성전자주식회사 선택적 실리사이드막의 형성 방법 및 이를 구비한 반도체소자
US6482703B1 (en) * 2001-09-28 2002-11-19 Taiwan Semiconductor Manufacturing Company Method for fabricating an electrostatic discharge device in a dual gate oxide process
US7585763B2 (en) * 2005-11-07 2009-09-08 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices using anti-reflective coating as implant blocking layer
US7557022B2 (en) * 2006-06-13 2009-07-07 Texas Instruments Incorporated Implantation of carbon and/or fluorine in NMOS fabrication
KR100808797B1 (ko) * 2006-08-29 2008-03-03 동부일렉트로닉스 주식회사 반도체 소자의 이온 주입 방법
KR100857453B1 (ko) * 2006-09-29 2008-09-08 한국전자통신연구원 저전압용 이미지 센서의 감광 픽셀
US7879639B2 (en) * 2007-04-13 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device to reduce dark current in image sensors
FR2939962B1 (fr) 2008-12-15 2011-03-18 Soitec Silicon On Insulator Procede d'amincissement d'une structure.
JP5672055B2 (ja) * 2011-02-23 2015-02-18 富士通セミコンダクター株式会社 半導体装置の製造方法
CN108231682B (zh) * 2016-12-22 2021-02-02 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN111370372B (zh) * 2020-04-22 2024-01-19 上海华虹宏力半导体制造有限公司 Cmos集成器件的制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894158A (en) * 1991-09-30 1999-04-13 Stmicroelectronics, Inc. Having halo regions integrated circuit device structure
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
FR2700418B1 (fr) * 1993-01-12 1995-04-07 France Telecom Composant électronique capable de résistance dynamique négative et procédé de fabrication correspondant.
JP3227983B2 (ja) * 1993-09-10 2001-11-12 ソニー株式会社 半導体装置及びその製造方法
US5480828A (en) * 1994-09-30 1996-01-02 Taiwan Semiconductor Manufacturing Corp. Ltd. Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process
US5780897A (en) * 1995-11-13 1998-07-14 Digital Equipment Corporation ESD protection clamp for mixed voltage I/O stages using NMOS transistors
US6075271A (en) * 1998-03-03 2000-06-13 Motorola, Inc. Semiconductor device inhibiting parasitic effects during electrostatic discharge

Also Published As

Publication number Publication date
JP2000232167A (ja) 2000-08-22
KR20000071335A (ko) 2000-11-25
DE60028847T2 (de) 2006-12-07
US6258644B1 (en) 2001-07-10
EP1026738B1 (de) 2006-06-21
TW459291B (en) 2001-10-11
EP1026738A3 (de) 2004-06-23
EP1026738A2 (de) 2000-08-09

Similar Documents

Publication Publication Date Title
DE60028847D1 (de) Verfahren mit reduzierter Maskenzahl für die Herstellung von Mischsspannung-CMOS mit Hochleistung-Transistoren und -I/O Transistoren von hoher Zuverlässigkeit
DE69932268D1 (de) Halbleiteranordnung aus vergossenem Kunststoff und Verfahren zu Ihrer Herstellung
DE60011199D1 (de) Harzzusammensetzung zur Einkapselung von Halbleitern, Halbleiteranordnungen die diese enthalten und Verfahren für die Herstellung von diesen Halbleiteranordnungen
DE60113579D1 (de) Integriertes Abwasserbehandlungsverfahren für die Herstellung von Nitroaromaten
DE59904603D1 (de) Verfahren zur Herstellung von Schaltungsanordnungen
DE60042008D1 (de) Herstellungsverfahren für dünnfilm-transistoren
DE69921714D1 (de) Photoempfindliche Harzzusammensetzung und Photoresist-Tinte für die Herstellung von gedruckten Leiterplatten
DE69434536D1 (de) Verfahren zur Herstellung von halbleitenden Wafern
DE68928847D1 (de) Fabrikationsverfahren für photonische, integrierte Schaltkreise
DE60015799D1 (de) Verfahren für die herstellung von tolterodine und deren analoga sowie im verfahren hergestellte zwischenprodukte
DE69723338D1 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE69902139D1 (de) Verfahren zur Herstellung von Salpetersäure
DE60142844D1 (de) Positive lichtempfindliche harzzusammensetzung, prozess zu ihrer herstellung und halbleiterbauelemente
DE69434937D1 (de) Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie
DE69307452D1 (de) Strahlungsempfindliche Harzzusammensetzung für die Herstellung von Mikrolinsen
DE69015494D1 (de) Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen.
DE50113689D1 (de) Verfahren zur schnellen Herstellung von hohlen Komponenten von Strömungsmaschinen für die Fertigungsentwicklung
DE69902638D1 (de) Integriertes verfahren zur herstellung von dien-komplexen
DE69608773D1 (de) Stahl für die Herstellung von teilbaren Maschinenteilen und Maschinenteile, hergestellt aus diesen Stahl
DE69417211D1 (de) Planariezierungsverfahren für die Herstellung von integrierten Schaltkreisen, insbesondere für nichtflüssige Halbleiterspeicheranordnungen
DE69517629D1 (de) Verfahren zur selektiven Herstellung von Halbleitergebieten
DE69232348D1 (de) Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung
DE59407872D1 (de) Verfahren zur Herstellung von Sinterformteilen
DE60030648D1 (de) Durch Elektroformung hergestellte Lichtblende und entsprechendes Herstellungsverfahren
DE69113673D1 (de) Halbleiterbauelement mit MOS-Transistoren und Verfahren zu dessen Herstellung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition