DE4022398A1 - Thermisch stabiles titan-silicid und verfahren zu dessen herstellung - Google Patents
Thermisch stabiles titan-silicid und verfahren zu dessen herstellungInfo
- Publication number
- DE4022398A1 DE4022398A1 DE4022398A DE4022398A DE4022398A1 DE 4022398 A1 DE4022398 A1 DE 4022398A1 DE 4022398 A DE4022398 A DE 4022398A DE 4022398 A DE4022398 A DE 4022398A DE 4022398 A1 DE4022398 A1 DE 4022398A1
- Authority
- DE
- Germany
- Prior art keywords
- film
- titanium
- titanium silicide
- silicide film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/62—Capacitors having potential barriers
- H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1183221A JPH0758773B2 (ja) | 1989-07-14 | 1989-07-14 | 半導体装置の製造方法及び半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE4022398A1 true DE4022398A1 (de) | 1991-01-24 |
| DE4022398C2 DE4022398C2 (enExample) | 1993-09-02 |
Family
ID=16131911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE4022398A Granted DE4022398A1 (de) | 1989-07-14 | 1990-07-13 | Thermisch stabiles titan-silicid und verfahren zu dessen herstellung |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6198143B1 (enExample) |
| JP (1) | JPH0758773B2 (enExample) |
| DE (1) | DE4022398A1 (enExample) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0517288A1 (en) * | 1991-04-29 | 1992-12-09 | Koninklijke Philips Electronics N.V. | Diffusion barrier enhancement in metallization structure for semiconductor device fabrication |
| EP0700081A3 (en) * | 1994-08-30 | 1997-07-02 | Texas Instruments Inc | Method of manufacturing a semiconductor device with integrated circuits using self-aligned silicide contacts for the zones |
| EP0863546A1 (fr) * | 1997-03-07 | 1998-09-09 | STMicroelectronics S.A. | Pseudofusible et application à un circuit d'établissement d'une bascule à la mise sous tension |
| WO2006061764A1 (en) * | 2004-12-06 | 2006-06-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2611726B2 (ja) * | 1993-10-07 | 1997-05-21 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP2699845B2 (ja) * | 1993-12-22 | 1998-01-19 | 日本電気株式会社 | 半導体装置の製造方法 |
| TW374196B (en) * | 1996-02-23 | 1999-11-11 | Semiconductor Energy Lab Co Ltd | Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same |
| US6028002A (en) * | 1996-05-15 | 2000-02-22 | Micron Technology, Inc. | Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients |
| US6348411B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method of making a contact structure |
| KR100304962B1 (ko) * | 1998-11-24 | 2001-10-20 | 김영환 | 텅스텐비트라인형성방법 |
| JP3472738B2 (ja) * | 1999-12-24 | 2003-12-02 | Necエレクトロニクス株式会社 | 回路製造方法、半導体装置 |
| JP2002043564A (ja) * | 2000-07-21 | 2002-02-08 | Mitsubishi Electric Corp | サリサイドトランジスタの製造方法、半導体記憶装置および半導体装置 |
| DE10056866C2 (de) * | 2000-11-16 | 2002-10-24 | Advanced Micro Devices Inc | Verfahren zur Bildung einer Ätzstoppschicht während der Herstellung eines Halbleiterbauteils |
| US20030168730A1 (en) * | 2002-03-08 | 2003-09-11 | Howard Davidson | Carbon foam heat exchanger for integrated circuit |
| US7485934B2 (en) * | 2005-10-25 | 2009-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated semiconductor structure for SRAM cells |
| JP5022614B2 (ja) * | 2006-03-20 | 2012-09-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5653577B2 (ja) * | 2007-08-31 | 2015-01-14 | アイメックImec | ゲルマナイド成長の改良方法およびそれにより得られたデバイス |
| JP2011176348A (ja) * | 2011-04-25 | 2011-09-08 | Renesas Electronics Corp | 半導体装置 |
| FR2990295B1 (fr) * | 2012-05-04 | 2016-11-25 | St Microelectronics Sa | Procede de formation de contacts de grille, de source et de drain sur un transistor mos |
| WO2015005933A1 (en) | 2013-07-12 | 2015-01-15 | Hewlett-Packard Development Company, L.P. | Thermal inkjet printhead stack with amorphous thin metal protective layer |
| US9469107B2 (en) | 2013-07-12 | 2016-10-18 | Hewlett-Packard Development Company, L.P. | Thermal inkjet printhead stack with amorphous metal resistor |
| US10177310B2 (en) | 2014-07-30 | 2019-01-08 | Hewlett Packard Enterprise Development Lp | Amorphous metal alloy electrodes in non-volatile device applications |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4276557A (en) * | 1978-12-29 | 1981-06-30 | Bell Telephone Laboratories, Incorporated | Integrated semiconductor circuit structure and method for making it |
| JPS62113421A (ja) * | 1985-11-13 | 1987-05-25 | Toshiba Corp | 半導体装置の製造方法 |
| JPS6390126A (ja) * | 1986-10-03 | 1988-04-21 | Hitachi Ltd | 半導体電極の形成方法 |
| US4905073A (en) * | 1987-06-22 | 1990-02-27 | At&T Bell Laboratories | Integrated circuit with improved tub tie |
| JPS644069A (en) * | 1987-06-26 | 1989-01-09 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4907048A (en) * | 1987-11-23 | 1990-03-06 | Xerox Corporation | Double implanted LDD transistor self-aligned with gate |
| US4949136A (en) * | 1988-06-09 | 1990-08-14 | University Of Connecticut | Submicron lightly doped field effect transistors |
| US4859278A (en) * | 1988-08-11 | 1989-08-22 | Xerox Corporation | Fabrication of high resistive loads utilizing a single level polycide process |
| JPH0258874A (ja) * | 1988-08-24 | 1990-02-28 | Nec Corp | 半導体集積回路装置 |
-
1989
- 1989-07-14 JP JP1183221A patent/JPH0758773B2/ja not_active Expired - Lifetime
-
1990
- 1990-07-13 DE DE4022398A patent/DE4022398A1/de active Granted
-
1996
- 1996-04-24 US US08/637,009 patent/US6198143B1/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| VLSI Metallizotion: Physics a. Techn., pp. 163-1711991, oder IEEE Tr. o. El. Dev., Vol. ED-27, pp. 1409-1416, Aug. 1980 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0517288A1 (en) * | 1991-04-29 | 1992-12-09 | Koninklijke Philips Electronics N.V. | Diffusion barrier enhancement in metallization structure for semiconductor device fabrication |
| EP0700081A3 (en) * | 1994-08-30 | 1997-07-02 | Texas Instruments Inc | Method of manufacturing a semiconductor device with integrated circuits using self-aligned silicide contacts for the zones |
| EP0863546A1 (fr) * | 1997-03-07 | 1998-09-09 | STMicroelectronics S.A. | Pseudofusible et application à un circuit d'établissement d'une bascule à la mise sous tension |
| FR2760563A1 (fr) * | 1997-03-07 | 1998-09-11 | Sgs Thomson Microelectronics | Pseudofusible et application a un circuit d'etablissement d'une bascule a la mise sous tension |
| WO2006061764A1 (en) * | 2004-12-06 | 2006-06-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4022398C2 (enExample) | 1993-09-02 |
| JPH0758773B2 (ja) | 1995-06-21 |
| US6198143B1 (en) | 2001-03-06 |
| JPH0346323A (ja) | 1991-02-27 |
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