DE3801220A1 - Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen - Google Patents

Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen

Info

Publication number
DE3801220A1
DE3801220A1 DE19883801220 DE3801220A DE3801220A1 DE 3801220 A1 DE3801220 A1 DE 3801220A1 DE 19883801220 DE19883801220 DE 19883801220 DE 3801220 A DE3801220 A DE 3801220A DE 3801220 A1 DE3801220 A1 DE 3801220A1
Authority
DE
Germany
Prior art keywords
counter
stages
group
counting
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19883801220
Other languages
German (de)
English (en)
Other versions
DE3801220C2 (fi
Inventor
Bernd Dipl Ing Kossack
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19883801220 priority Critical patent/DE3801220A1/de
Publication of DE3801220A1 publication Critical patent/DE3801220A1/de
Application granted granted Critical
Publication of DE3801220C2 publication Critical patent/DE3801220C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318527—Test of counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE19883801220 1988-01-18 1988-01-18 Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen Granted DE3801220A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19883801220 DE3801220A1 (de) 1988-01-18 1988-01-18 Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19883801220 DE3801220A1 (de) 1988-01-18 1988-01-18 Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen

Publications (2)

Publication Number Publication Date
DE3801220A1 true DE3801220A1 (de) 1989-07-27
DE3801220C2 DE3801220C2 (fi) 1991-10-17

Family

ID=6345447

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883801220 Granted DE3801220A1 (de) 1988-01-18 1988-01-18 Vielstufiger binaerzaehler mit einer ausstattung zur durchfuehrung von testlaeufen

Country Status (1)

Country Link
DE (1) DE3801220A1 (fi)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0395209A2 (en) * 1989-04-26 1990-10-31 Advanced Micro Devices, Inc. Method and apparatus for testing a binary counter
US5381453A (en) * 1994-02-09 1995-01-10 Zilog, Inc. Efficient functional test scheme incorporated in a programmable duration binary counter
DE19522839A1 (de) * 1995-06-23 1997-01-02 Telefunken Microelectron Verfahren zum Testen von Impulszählern

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4214841C2 (de) * 1992-05-05 1994-10-06 Telefunken Microelectron Schlatungsanordnung für den Funktionstest eines in einem Schaltkreis integrierten Zeitglieds

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924144A (en) * 1973-05-11 1975-12-02 Ibm Method for testing logic chips and logic chips adapted therefor
JPS62252214A (ja) * 1986-04-25 1987-11-04 Hitachi Ltd 診断回路付非同期式カウンタ回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924144A (en) * 1973-05-11 1975-12-02 Ibm Method for testing logic chips and logic chips adapted therefor
JPS62252214A (ja) * 1986-04-25 1987-11-04 Hitachi Ltd 診断回路付非同期式カウンタ回路

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patents Abstracts of Japan, E-602 April 20, 1988 Vol.12/No.127 *
WILLIAMS, T.: Design for Testability - A Survey. In: JEEE Transactions on Computers, Vol. C-31, No.1, Januar 1982, S. 2-15 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0395209A2 (en) * 1989-04-26 1990-10-31 Advanced Micro Devices, Inc. Method and apparatus for testing a binary counter
EP0395209A3 (en) * 1989-04-26 1991-08-21 Advanced Micro Devices, Inc. Method and apparatus for testing a binary counter
US5381453A (en) * 1994-02-09 1995-01-10 Zilog, Inc. Efficient functional test scheme incorporated in a programmable duration binary counter
DE19522839A1 (de) * 1995-06-23 1997-01-02 Telefunken Microelectron Verfahren zum Testen von Impulszählern
DE19522839C2 (de) * 1995-06-23 2003-12-18 Atmel Germany Gmbh Verfahren zum Testen von Impulszählern

Also Published As

Publication number Publication date
DE3801220C2 (fi) 1991-10-17

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee