DE3790800C2 - Verfahren zum Herstellen selbstausgerichteter Halbleiterelemente - Google Patents

Verfahren zum Herstellen selbstausgerichteter Halbleiterelemente

Info

Publication number
DE3790800C2
DE3790800C2 DE3790800A DE3790800A DE3790800C2 DE 3790800 C2 DE3790800 C2 DE 3790800C2 DE 3790800 A DE3790800 A DE 3790800A DE 3790800 A DE3790800 A DE 3790800A DE 3790800 C2 DE3790800 C2 DE 3790800C2
Authority
DE
Germany
Prior art keywords
protective layer
window
substrate
aligned
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3790800A
Other languages
German (de)
English (en)
Other versions
DE3790800T1 (https=
Inventor
Peter Vance Gray
Bantval Jayant Baliga
Mike Fu Shing Chang
George Charles Pifer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Application granted granted Critical
Publication of DE3790800C2 publication Critical patent/DE3790800C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0102—Manufacture or treatment of thyristors having built-in components, e.g. thyristor having built-in diode
    • H10D84/0105—Manufacture or treatment of thyristors having built-in components, e.g. thyristor having built-in diode the built-in components being field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE3790800A 1986-12-05 1987-12-03 Verfahren zum Herstellen selbstausgerichteter Halbleiterelemente Expired - Fee Related DE3790800C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93869386A 1986-12-05 1986-12-05
PCT/US1987/003106 WO1988004472A1 (en) 1986-12-05 1987-12-03 Method of fabricating self aligned semiconductor devices

Publications (1)

Publication Number Publication Date
DE3790800C2 true DE3790800C2 (de) 1999-08-12

Family

ID=25471812

Family Applications (2)

Application Number Title Priority Date Filing Date
DE3790800A Expired - Fee Related DE3790800C2 (de) 1986-12-05 1987-12-03 Verfahren zum Herstellen selbstausgerichteter Halbleiterelemente
DE19873790800 Pending DE3790800T1 (https=) 1986-12-05 1987-12-03

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19873790800 Pending DE3790800T1 (https=) 1986-12-05 1987-12-03

Country Status (3)

Country Link
JP (1) JPH0783124B2 (https=)
DE (2) DE3790800C2 (https=)
WO (1) WO1988004472A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277135A (ja) * 1988-09-13 1990-03-16 Nec Corp 半導体装置の製造方法
EP0769811A1 (en) * 1995-10-19 1997-04-23 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Method of fabricating self aligned DMOS devices
JP5514726B2 (ja) * 2008-08-26 2014-06-04 本田技研工業株式会社 接合型半導体装置およびその製造方法
CN111999632B (zh) * 2019-05-27 2023-02-03 合肥晶合集成电路股份有限公司 Pn结样品的获取方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443931A (en) * 1982-06-28 1984-04-24 General Electric Company Method of fabricating a semiconductor device with a base region having a deep portion
US4466176A (en) * 1982-08-09 1984-08-21 General Electric Company Process for manufacturing insulated-gate semiconductor devices with integral shorts
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Electronic Design 10, 1986, pp. 45-48 *
Halbleitertechnologie, I. Ruge, Springer Verlag, 1975, S. 298-299 *
IEEE El. Dev. Lett., EDL-6, 1985, pp. 413-415 *
IEEE Elektron Device Letters, Vol. EDL-5, No. 11, November 1984 *
Solid State Techn. 1985, pp. 121-128 *

Also Published As

Publication number Publication date
DE3790800T1 (https=) 1989-01-19
WO1988004472A1 (en) 1988-06-16
JPS63503027A (ja) 1988-11-02
JPH0783124B2 (ja) 1995-09-06

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H01L 29/78

8128 New person/name/address of the agent

Representative=s name: SIEB, R., DIPL.-CHEM. DR. RER. NAT., PAT.-ANW., 69

8125 Change of the main classification

Ipc: H01L 21/336

8607 Notification of search results after publication
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee