DE3783006D1 - Schaltungsanordnung fuer einen differenzverstaerker. - Google Patents

Schaltungsanordnung fuer einen differenzverstaerker.

Info

Publication number
DE3783006D1
DE3783006D1 DE8787402007T DE3783006T DE3783006D1 DE 3783006 D1 DE3783006 D1 DE 3783006D1 DE 8787402007 T DE8787402007 T DE 8787402007T DE 3783006 T DE3783006 T DE 3783006T DE 3783006 D1 DE3783006 D1 DE 3783006D1
Authority
DE
Germany
Prior art keywords
differential amplifier
circuit arrangement
arrangement
circuit
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787402007T
Other languages
English (en)
Other versions
DE3783006T2 (de
Inventor
Kay Tohyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3783006D1 publication Critical patent/DE3783006D1/de
Publication of DE3783006T2 publication Critical patent/DE3783006T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
    • H03K19/018542—Interface arrangements of Schottky barrier type [MESFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45104—A diode being used as clamping element at the loading circuit of the dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45106—A diode being used as clamping element at the output of the dif amp

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
DE8787402007T 1986-09-13 1987-09-08 Schaltungsanordnung fuer einen differenzverstaerker. Expired - Fee Related DE3783006T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61216755A JP2559032B2 (ja) 1986-09-13 1986-09-13 差動増幅回路

Publications (2)

Publication Number Publication Date
DE3783006D1 true DE3783006D1 (de) 1993-01-21
DE3783006T2 DE3783006T2 (de) 1993-04-15

Family

ID=16693411

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787402007T Expired - Fee Related DE3783006T2 (de) 1986-09-13 1987-09-08 Schaltungsanordnung fuer einen differenzverstaerker.

Country Status (5)

Country Link
US (1) US4777451A (de)
EP (1) EP0263006B1 (de)
JP (1) JP2559032B2 (de)
KR (1) KR900009192B1 (de)
DE (1) DE3783006T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924116A (en) * 1988-01-19 1990-05-08 Honeywell Inc. Feedback source coupled FET logic
TW307064B (de) * 1993-09-08 1997-06-01 Advanced Micro Devices Inc
JPH07142942A (ja) * 1993-11-18 1995-06-02 Nec Corp 差動増幅器
WO1995030279A1 (en) * 1994-04-29 1995-11-09 Analog Devices, Inc. Charge redistribution analog-to-digital converter with system calibration
US5600275A (en) * 1994-04-29 1997-02-04 Analog Devices, Inc. Low-voltage CMOS comparator with offset cancellation
US5600322A (en) * 1994-04-29 1997-02-04 Analog Devices, Inc. Low-voltage CMOS analog-to-digital converter
JP3158000B2 (ja) * 1994-12-26 2001-04-23 沖電気工業株式会社 バイアス回路
US5668551A (en) * 1995-01-18 1997-09-16 Analog Devices, Inc. Power-up calibration of charge redistribution analog-to-digital converter
US5621409A (en) * 1995-02-15 1997-04-15 Analog Devices, Inc. Analog-to-digital conversion with multiple charge balance conversions
US5703519A (en) * 1996-01-30 1997-12-30 Analog Devices, Inc. Drive circuit and method for controlling the cross point levels of a differential CMOS switch drive signal
GB2313725B (en) * 1996-05-31 1998-04-08 Ebrahim Bushehri A circuit arrangement for a logic gate
US6366168B1 (en) * 2000-03-20 2002-04-02 Marvell International Ltd. Efficient ground noise and common-mode suppression network
JP2005045702A (ja) * 2003-07-25 2005-02-17 Matsushita Electric Ind Co Ltd 差動増幅回路および差動増幅回路を搭載したテスト回路
JP5764742B2 (ja) * 2010-05-17 2015-08-19 パナソニックＩｐマネジメント株式会社 接合型電界効果トランジスタ、その製造方法及びアナログ回路
JP5238856B2 (ja) * 2011-06-23 2013-07-17 ルネサスエレクトロニクス株式会社 差動増幅回路及びａ／ｄ変換器
US8369818B2 (en) * 2011-06-27 2013-02-05 Broadcom Corporation Low noise amplifier protection using a clamping device
CN111208401B (zh) * 2018-11-22 2023-01-31 宁波飞芯电子科技有限公司 一种钳位光电二极管的测试方法以及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508084A (en) * 1967-10-06 1970-04-21 Texas Instruments Inc Enhancement-mode mos circuitry
US3898477A (en) * 1974-06-03 1975-08-05 Motorola Inc Self ratioing input buffer circuit
US3970951A (en) * 1975-11-12 1976-07-20 International Business Machines Corporation Differential amplifier with constant gain
US4393315A (en) * 1981-05-18 1983-07-12 Sperry Corporation High-gain stabilized converter
JPS59151510A (ja) * 1983-02-18 1984-08-30 Hitachi Ltd Ｃ−ｍｏｓ負荷型増幅器
JPS6123403A (ja) * 1984-07-11 1986-01-31 Hitachi Ltd 差動増幅回路
DE3663764D1 (en) * 1986-03-21 1989-07-06 Itt Ind Gmbh Deutsche Differential amplifier with nmos transistors

Also Published As

Publication number Publication date
KR900009192B1 (ko) 1990-12-24
EP0263006B1 (de) 1992-12-09
JPS6372207A (ja) 1988-04-01
DE3783006T2 (de) 1993-04-15
KR880004638A (ko) 1988-06-07
JP2559032B2 (ja) 1996-11-27
EP0263006A1 (de) 1988-04-06
US4777451A (en) 1988-10-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee