DE3751313T2 - Verfahren zur Herstellung von CMOS- und Hochspannungs-elektronische-bauelemente beinhaltende Halbleiterbauelemente. - Google Patents

Verfahren zur Herstellung von CMOS- und Hochspannungs-elektronische-bauelemente beinhaltende Halbleiterbauelemente.

Info

Publication number
DE3751313T2
DE3751313T2 DE3751313T DE3751313T DE3751313T2 DE 3751313 T2 DE3751313 T2 DE 3751313T2 DE 3751313 T DE3751313 T DE 3751313T DE 3751313 T DE3751313 T DE 3751313T DE 3751313 T2 DE3751313 T2 DE 3751313T2
Authority
DE
Germany
Prior art keywords
cmos
production
containing semiconductor
voltage electronic
electronic components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751313T
Other languages
English (en)
Other versions
DE3751313D1 (de
Inventor
Antonio Andreini
Claudio Contiero
Paola Galbiati
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE3751313D1 publication Critical patent/DE3751313D1/de
Application granted granted Critical
Publication of DE3751313T2 publication Critical patent/DE3751313T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
DE3751313T 1986-03-27 1987-03-24 Verfahren zur Herstellung von CMOS- und Hochspannungs-elektronische-bauelemente beinhaltende Halbleiterbauelemente. Expired - Fee Related DE3751313T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT19906/86A IT1188465B (it) 1986-03-27 1986-03-27 Rpocedimento per la fabbricazione di circuiti integrati a semiconduttore includenti dispositiv cmos e dispositivi elettronici ad alta tensione

Publications (2)

Publication Number Publication Date
DE3751313D1 DE3751313D1 (de) 1995-06-29
DE3751313T2 true DE3751313T2 (de) 1996-02-01

Family

ID=11162231

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751313T Expired - Fee Related DE3751313T2 (de) 1986-03-27 1987-03-24 Verfahren zur Herstellung von CMOS- und Hochspannungs-elektronische-bauelemente beinhaltende Halbleiterbauelemente.

Country Status (5)

Country Link
US (1) US4892836A (de)
EP (1) EP0239060B1 (de)
JP (1) JP2814079B2 (de)
DE (1) DE3751313T2 (de)
IT (1) IT1188465B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
IT1217323B (it) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa Struttura integrata di transistor bipolare di potenza di alta tensione e di transistor mos di potenza di bassa tensione nella configurazione"emitter switching"e relativo processo di fabbricazione
US5011784A (en) * 1988-01-21 1991-04-30 Exar Corporation Method of making a complementary BiCMOS process with isolated vertical PNP transistors
US5116777A (en) * 1990-04-30 1992-05-26 Sgs-Thomson Microelectronics, Inc. Method for fabricating semiconductor devices by use of an N+ buried layer for complete isolation
US5446300A (en) * 1992-11-04 1995-08-29 North American Philips Corporation Semiconductor device configuration with multiple HV-LDMOS transistors and a floating well circuit
DE69431181D1 (de) * 1994-05-19 2002-09-19 Cons Ric Microelettronica Integrierte Leistungsschaltung ("PIC") und Verfahren zur Herstellung derselben
EP0751573A1 (de) * 1995-06-30 1997-01-02 STMicroelectronics S.r.l. Integrierte Leistungsschaltung und Verfahren zur Herstellung derselben
US5602046A (en) * 1996-04-12 1997-02-11 National Semiconductor Corporation Integrated zener diode protection structures and fabrication methods for DMOS power devices
US5770880A (en) * 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
JP5096708B2 (ja) * 2006-07-28 2012-12-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8106487B2 (en) 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US30282A (en) * 1860-10-09 Quartz crusher and amalgamator
US4054899A (en) * 1970-09-03 1977-10-18 Texas Instruments Incorporated Process for fabricating monolithic circuits having matched complementary transistors and product
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
US4325180A (en) * 1979-02-15 1982-04-20 Texas Instruments Incorporated Process for monolithic integration of logic, control, and high voltage interface circuitry
US4346512A (en) * 1980-05-05 1982-08-31 Raytheon Company Integrated circuit manufacturing method
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
JPH061816B2 (ja) * 1983-09-30 1994-01-05 日本電気株式会社 半導体装置の製造方法
US4609413A (en) * 1983-11-18 1986-09-02 Motorola, Inc. Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique
IT1214806B (it) * 1984-09-21 1990-01-18 Ates Componenti Elettron Dispositivo integrato monolitico di potenza e semiconduttore
FR2571178B1 (fr) * 1984-09-28 1986-11-21 Thomson Csf Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication

Also Published As

Publication number Publication date
DE3751313D1 (de) 1995-06-29
JPS62237757A (ja) 1987-10-17
US4892836A (en) 1990-01-09
EP0239060A2 (de) 1987-09-30
JP2814079B2 (ja) 1998-10-22
IT8619906A1 (it) 1987-09-27
IT1188465B (it) 1988-01-14
IT8619906A0 (it) 1986-03-27
EP0239060A3 (en) 1989-11-15
EP0239060B1 (de) 1995-05-24

Similar Documents

Publication Publication Date Title
DE69031447D1 (de) Verfahren zur Herstellung von MIS-Halbleiterbauelementen
DE3789881D1 (de) Verfahren zur Herstellung von Photomasken und Photomaske.
DE3750076T2 (de) Verfahren zur Veränderung der Eigenschften von Halbleitern.
DE3786639T2 (de) Verfahren zur Herstellung von Entwicklerpulver.
DE69014707D1 (de) Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren.
DE3788399T2 (de) Verfahren zur Herstellung von eingekapseltem Toner.
DE3787937T2 (de) Verfahren zur Herstellung von metallisierten Bildern.
DE3751018T2 (de) Verfahren zur Herstellung von direkt-positiven Bildern.
DE3881732T2 (de) Verfahren zur Herstellung von Früchtechips.
DE3750318D1 (de) Verfahren zur Herstellung von Halosilanen.
DE3751313T2 (de) Verfahren zur Herstellung von CMOS- und Hochspannungs-elektronische-bauelemente beinhaltende Halbleiterbauelemente.
DE3789680D1 (de) Verfahren zur Herstellung von Halbleiterbauelementen.
DE3850519T2 (de) Vorrichtung zur Herstellung von Halbleiter-Bauelementen.
DE3855580T2 (de) Verfahren zur Herstellung von Polyparaphenylensulfiden
DE3883407D1 (de) Verfahren zur Herstellung von Fruit-Chips.
DE3789412T2 (de) Verfahren zur Herstellung von 3-Alkoxymethylcephalosporinen.
DE69018307D1 (de) Verfahren zur Herstellung von Kontakten in Halbleiterbauelementen.
DE69011567D1 (de) Verfahren zur Herstellung von elektronischen und optischen Komponenten.
DE19675009I2 (de) Verfahren zur Herstellung von Hylan und Hylanverbindungen.
DE68908681D1 (de) Verfahren zur Herstellung von feinpulvrigem beta-Sialon.
ATE51004T1 (de) Verfahren zur herstellung von 9(11)dehydroandrostanen.
ATE48393T1 (de) Einlegesohlen und bestandteile von sohlen sowie verfahren zur herstellung derselben.
ATE80185T1 (de) Verfahren und vorrichtung zur herstellung von ozon.
ATE24518T1 (de) Verfahren zur herstellung von ribavirin.
ATE56492T1 (de) Verfahren zur herstellung von melaminharzfolien.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, MAILAND

8339 Ceased/non-payment of the annual fee