DE3750130D1 - Halbleiter-Heterostruktur mit einem Bereich mit veränderlicher SnSi Verbindung. - Google Patents

Halbleiter-Heterostruktur mit einem Bereich mit veränderlicher SnSi Verbindung.

Info

Publication number
DE3750130D1
DE3750130D1 DE3750130T DE3750130T DE3750130D1 DE 3750130 D1 DE3750130 D1 DE 3750130D1 DE 3750130 T DE3750130 T DE 3750130T DE 3750130 T DE3750130 T DE 3750130T DE 3750130 D1 DE3750130 D1 DE 3750130D1
Authority
DE
Germany
Prior art keywords
snsi
variable
area
connection
semiconductor heterostructure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3750130T
Other languages
English (en)
Other versions
DE3750130T2 (de
Inventor
Sergey Luryi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE3750130D1 publication Critical patent/DE3750130D1/de
Publication of DE3750130T2 publication Critical patent/DE3750130T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02452—Group 14 semiconducting materials including tin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02535—Group 14 semiconducting materials including tin
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/16—Superlattice
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/169—Vacuum deposition, e.g. including molecular beam epitaxy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/936—Graded energy gap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE3750130T 1986-12-29 1987-12-11 Halbleiter-Heterostruktur mit einem Bereich mit veränderlicher SnSi Verbindung. Expired - Fee Related DE3750130T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/947,051 US4769341A (en) 1986-12-29 1986-12-29 Method of fabricating non-silicon materials on silicon substrate using an alloy of Sb and Group IV semiconductors

Publications (2)

Publication Number Publication Date
DE3750130D1 true DE3750130D1 (de) 1994-07-28
DE3750130T2 DE3750130T2 (de) 1994-11-17

Family

ID=25485434

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750130T Expired - Fee Related DE3750130T2 (de) 1986-12-29 1987-12-11 Halbleiter-Heterostruktur mit einem Bereich mit veränderlicher SnSi Verbindung.

Country Status (4)

Country Link
US (1) US4769341A (de)
EP (1) EP0279989B1 (de)
JP (1) JPH069192B2 (de)
DE (1) DE3750130T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2569058B2 (ja) * 1987-07-10 1997-01-08 株式会社日立製作所 半導体装置
JP2649936B2 (ja) * 1988-03-01 1997-09-03 富士通株式会社 歪超格子バッファ
US4948752A (en) * 1988-08-10 1990-08-14 Itt Corporation Method of making sagfets on buffer layers
JPH02170413A (ja) * 1988-12-22 1990-07-02 Fujitsu Ltd 化合物半導体装置
US5021360A (en) * 1989-09-25 1991-06-04 Gte Laboratories Incorporated Method of farbicating highly lattice mismatched quantum well structures
US5628834A (en) * 1990-03-23 1997-05-13 International Business Machines Corporation Surfactant-enhanced epitaxy
US5316615A (en) * 1990-03-23 1994-05-31 International Business Machines Corporation Surfactant-enhanced epitaxy
US5997638A (en) * 1990-03-23 1999-12-07 International Business Machines Corporation Localized lattice-mismatch-accomodation dislocation network epitaxy
US5061973A (en) * 1990-04-27 1991-10-29 The United States Of America As Represented By The Secretary Of The Navy Semiconductor heterojunction device with graded bandgap
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
FR2666172B1 (fr) * 1990-08-24 1997-05-16 Thomson Csf Transistor de puissance et procede de realisation.
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Heteroepitaxial layers with low defect density and arbitrary network parameter
US5548128A (en) * 1994-12-14 1996-08-20 The United States Of America As Represented By The Secretary Of The Air Force Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates
US5741724A (en) * 1996-12-27 1998-04-21 Motorola Method of growing gallium nitride on a spinel substrate
US6037614A (en) * 1997-03-07 2000-03-14 California Institute Of Technology Methods for manufacturing group IV element alloy semiconductor materials and devices that include such materials
US7598513B2 (en) * 2003-06-13 2009-10-06 Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University, A Corporate Body Organized Under Arizona Law SixSnyGe1-x-y and related alloy heterostructures based on Si, Ge and Sn
WO2005015609A2 (en) * 2003-06-13 2005-02-17 Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University Sixsnyge1-x-y and related alloy heterostructures based on si, ge and sn
US6897471B1 (en) * 2003-11-28 2005-05-24 The United States Of America As Represented By The Secretary Of The Air Force Strain-engineered direct-gap Ge/SnxGe1-x heterodiode and multi-quantum-well photodetectors, laser, emitters and modulators grown on SnySizGe1-y-z-buffered silicon
US7282425B2 (en) * 2005-01-31 2007-10-16 International Business Machines Corporation Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
KR100932821B1 (ko) * 2005-03-11 2009-12-21 아리조나 보드 오브 리전트스, 아리조나주의 아리조나 주립대 대행법인 게르마늄규소주석계 화합물, 주형 및 반도체 구조물
JP5238189B2 (ja) * 2007-05-17 2013-07-17 国立大学法人名古屋大学 伸張歪ゲルマニウム薄膜の作製方法、伸張歪ゲルマニウム薄膜、及び多層膜構造体
EP2691977B1 (de) * 2011-03-31 2019-06-05 IMEC vzw Verfahren zur herstellung eines monokristallinen zinnhaltigen halbleitermaterials
JP5928864B2 (ja) * 2011-05-23 2016-06-01 国立大学法人名古屋大学 多層膜構造体及びその形成方法
US8647439B2 (en) 2012-04-26 2014-02-11 Applied Materials, Inc. Method of epitaxial germanium tin alloy surface preparation
JP2015156430A (ja) * 2014-02-20 2015-08-27 国立大学法人名古屋大学 半導体結晶の製造方法、半導体結晶及び半導体デバイス
US9142406B1 (en) * 2014-05-02 2015-09-22 Translucent, Inc. III-N material grown on ErAlN buffer on Si substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3626328A (en) * 1969-04-01 1971-12-07 Ibm Semiconductor bulk oscillator
US3626257A (en) * 1969-04-01 1971-12-07 Ibm Semiconductor device with superlattice region
FR2225207B1 (de) * 1973-04-16 1978-04-21 Ibm
US4120706A (en) * 1977-09-16 1978-10-17 Harris Corporation Heteroepitaxial deposition of gap on silicon substrates
US4180825A (en) * 1977-09-16 1979-12-25 Harris Corporation Heteroepitaxial deposition of GaP on silicon substrates
JPS6029295B2 (ja) * 1979-08-16 1985-07-10 舜平 山崎 非単結晶被膜形成法
JPS5696834A (en) * 1979-12-28 1981-08-05 Mitsubishi Monsanto Chem Co Compound semiconductor epitaxial wafer and manufacture thereof
GB2084396B (en) * 1980-09-18 1984-06-13 Standard Telephones Cables Ltd A-tin semiconductor device
JPS5929484A (ja) * 1982-08-12 1984-02-16 Fujitsu Ltd 半導体発光装置
US4616241A (en) * 1983-03-22 1986-10-07 The United States Of America As Represented By The United States Department Of Energy Superlattice optical device
US4529455A (en) * 1983-10-28 1985-07-16 At&T Bell Laboratories Method for epitaxially growing Gex Si1-x layers on Si utilizing molecular beam epitaxy
US4697202A (en) * 1984-02-02 1987-09-29 Sri International Integrated circuit having dislocation free substrate
JPH0728080B2 (ja) * 1984-09-25 1995-03-29 日本電気株式会社 半導体超格子構造体

Also Published As

Publication number Publication date
EP0279989A3 (en) 1990-03-07
EP0279989B1 (de) 1994-06-22
US4769341A (en) 1988-09-06
DE3750130T2 (de) 1994-11-17
JPS63169717A (ja) 1988-07-13
EP0279989A2 (de) 1988-08-31
JPH069192B2 (ja) 1994-02-02

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Legal Events

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8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee