DE3743515A1 - Hochleistungs-mikroprozessor - Google Patents

Hochleistungs-mikroprozessor

Info

Publication number
DE3743515A1
DE3743515A1 DE19873743515 DE3743515A DE3743515A1 DE 3743515 A1 DE3743515 A1 DE 3743515A1 DE 19873743515 DE19873743515 DE 19873743515 DE 3743515 A DE3743515 A DE 3743515A DE 3743515 A1 DE3743515 A1 DE 3743515A1
Authority
DE
Germany
Prior art keywords
microprocessor
high performance
references
performance microprocessor
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19873743515
Other languages
English (en)
Inventor
Don Alpert
Gigi Baror
Moti Beck
Zeev Bikowski
Dan Biran
Elliot Cohen
Lev Epstein
Nissan Gellerman
Yair Hadas
Yoav Hollander
Benny Konstantin
Jonathan Levy
Reuven Marko
Benny Maytal
Yaakov Milstein
Aharon Ostrer
Rami Saban
Alon Shacham
Boaz Shahar
Yom-Tov Sidi
Uri Weiser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE3743515A1 publication Critical patent/DE3743515A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Microcomputers (AREA)
DE19873743515 1987-01-22 1987-12-22 Hochleistungs-mikroprozessor Ceased DE3743515A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US601687A 1987-01-22 1987-01-22

Publications (1)

Publication Number Publication Date
DE3743515A1 true DE3743515A1 (de) 1988-08-04

Family

ID=21718873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873743515 Ceased DE3743515A1 (de) 1987-01-22 1987-12-22 Hochleistungs-mikroprozessor

Country Status (4)

Country Link
US (1) US5438670A (de)
JP (1) JPS63193230A (de)
DE (1) DE3743515A1 (de)
GB (2) GB2200483B (de)

Cited By (1)

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DE3933849A1 (de) * 1988-10-11 1990-06-21 Mips Computer Systems Inc Prozessorgesteuerte schnittstelle

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US5925125A (en) * 1993-06-24 1999-07-20 International Business Machines Corporation Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
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US5715425A (en) * 1996-02-22 1998-02-03 Sun Microsystems, Inc. Apparatus and method for prefetching data into an external cache
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US5913923A (en) * 1996-12-06 1999-06-22 National Semiconductor Corporation Multiple bus master computer system employing a shared address translation unit
US5987568A (en) * 1997-01-10 1999-11-16 3Com Corporation Apparatus and method for operably connecting a processor cache and a cache controller to a digital signal processor
JPH1153260A (ja) * 1997-08-06 1999-02-26 Nec Corp キャッシュメモリー内蔵半導体装置
US6044454A (en) * 1998-02-19 2000-03-28 International Business Machines Corporation IEEE compliant floating point unit
EP1046998A1 (de) * 1999-04-22 2000-10-25 Texas Instruments Incorporated Digitale Signalprozessoren mit virtueller Addressierung
US20020144235A1 (en) * 2001-03-30 2002-10-03 Charles Simmers Debugging embedded systems
US7027446B2 (en) * 2001-07-18 2006-04-11 P-Cube Ltd. Method and apparatus for set intersection rule matching
US6587929B2 (en) * 2001-07-31 2003-07-01 Ip-First, L.L.C. Apparatus and method for performing write-combining in a pipelined microprocessor using tags
JP2004062319A (ja) * 2002-07-25 2004-02-26 Renesas Technology Corp データ処理装置
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US20050081015A1 (en) * 2003-09-30 2005-04-14 Barry Peter J. Method and apparatus for adapting write instructions for an expansion bus
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7458078B2 (en) * 2003-11-06 2008-11-25 International Business Machines Corporation Apparatus and method for autonomic hardware assisted thread stack tracking
US7895382B2 (en) 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7415705B2 (en) 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US20060136608A1 (en) * 2004-12-22 2006-06-22 Gilbert Jeffrey D System and method for control registers accessed via private operations
US7437517B2 (en) * 2005-01-11 2008-10-14 International Business Machines Corporation Methods and arrangements to manage on-chip memory to reduce memory latency
JP4644569B2 (ja) * 2005-09-02 2011-03-02 富士通セミコンダクター株式会社 複数チップの起動方法
CN101470661B (zh) * 2007-12-28 2012-03-14 鸿富锦精密工业（深圳）有限公司 计算机程序除错系统及方法
US8447962B2 (en) * 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
CN104126173A (zh) * 2011-12-23 2014-10-29 英特尔公司 不会引起密码应用的算术标志的三输入操作数向量add指令
GB2514107B (en) * 2013-05-13 2020-07-29 Advanced Risc Mach Ltd Page table data management
US10606596B2 (en) 2013-07-15 2020-03-31 Texas Instruments Incorporated Cache preload operations using streaming engine
US10599433B2 (en) * 2013-07-15 2020-03-24 Texas Instruments Incorported Cache management operations using streaming engine
GB2519801A (en) 2013-10-31 2015-05-06 Ibm Computing architecture and method for processing data
US10489185B2 (en) * 2017-03-17 2019-11-26 Nicira, Inc. Hypervisor-assisted approach for locating operating system data structures based on attribute matching
US20180267818A1 (en) * 2017-03-17 2018-09-20 Nicira, Inc. Hypervisor-assisted approach for locating operating system data structures based on notification data

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EP0192578A2 (de) * 1985-02-22 1986-08-27 Intergraph Corporation Mehrbusanordnung mit einem Mikroprozessor mit getrennten Befehls- und Datenschnittstellen und Cachespeichern

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3933849A1 (de) * 1988-10-11 1990-06-21 Mips Computer Systems Inc Prozessorgesteuerte schnittstelle

Also Published As

Publication number Publication date
GB2200483B (en) 1991-10-16
GB2200483A (en) 1988-08-03
JPS63193230A (ja) 1988-08-10
GB9115026D0 (en) 1991-08-28
GB8729326D0 (en) 1988-01-27
US5438670A (en) 1995-08-01

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: RICHTER, J., DIPL.-ING., 1000 BERLIN GERBAULET, H.

8110 Request for examination paragraph 44
8131 Rejection