BR9810768A - Processo de manuseio de instruções especìficas, e, processador - Google Patents

Processo de manuseio de instruções especìficas, e, processador

Info

Publication number
BR9810768A
BR9810768A BR9810768-2A BR9810768A BR9810768A BR 9810768 A BR9810768 A BR 9810768A BR 9810768 A BR9810768 A BR 9810768A BR 9810768 A BR9810768 A BR 9810768A
Authority
BR
Brazil
Prior art keywords
processor
instructions
read
instruction buffer
specific instructions
Prior art date
Application number
BR9810768-2A
Other languages
English (en)
Inventor
Carl Tobias Roos
Lundstroem Lars-Erik
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9810768A publication Critical patent/BR9810768A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

"PROCESSO DE MANUSEIO DE INSTRUçõES ESPECìFICAS, E, PROCESSADOR" A presente invenção refere-se a um processo de manuseio de instruções de oscilação condicional em um processador de computador (1). O espaço é destinado em um buffer de instrução (3) para as instruções respectivas lidas para dentro do processador. Esses espaços recebem uma ordem que corresponde à ordem na qual as instruções foram lidas seq³encialmente. A última posição no buffer de instrução constitui uma posição de leitura (4). Os resultados obtidos quando do processamento de instruções respectivas podem ser salvados em espaços destinados a essas instruções no buffer de instrução (3), a partir do qual os resultados podem ser finalmente lidos a partir da posição de leitura (4).
BR9810768-2A 1997-07-21 1998-07-07 Processo de manuseio de instruções especìficas, e, processador BR9810768A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9702762A SE510295C2 (sv) 1997-07-21 1997-07-21 Metod vid processor för att hantera villkorade hoppinstruktioner samt processor anpassad att verka enligt den angivna metoden
PCT/SE1998/001334 WO1999004335A2 (en) 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps

Publications (1)

Publication Number Publication Date
BR9810768A true BR9810768A (pt) 2000-08-15

Family

ID=20407793

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9810768-2A BR9810768A (pt) 1997-07-21 1998-07-07 Processo de manuseio de instruções especìficas, e, processador

Country Status (8)

Country Link
EP (1) EP0998701A2 (pt)
JP (1) JP2001510916A (pt)
KR (1) KR20010022065A (pt)
CN (1) CN1271434A (pt)
AU (1) AU8365298A (pt)
BR (1) BR9810768A (pt)
SE (1) SE510295C2 (pt)
WO (1) WO1999004335A2 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US9952869B2 (en) 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
EP2367102B1 (en) 2010-02-11 2013-04-10 Nxp B.V. Computer processor and method with increased security properties

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
CA1285657C (en) * 1986-01-29 1991-07-02 Douglas W. Clark Apparatus and method for execution of branch instructions
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
SE509499C2 (sv) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur

Also Published As

Publication number Publication date
SE510295C2 (sv) 1999-05-10
KR20010022065A (ko) 2001-03-15
SE9702762D0 (sv) 1997-07-21
AU8365298A (en) 1999-02-10
EP0998701A2 (en) 2000-05-10
WO1999004335A3 (en) 1999-04-08
WO1999004335A2 (en) 1999-01-28
JP2001510916A (ja) 2001-08-07
CN1271434A (zh) 2000-10-25
SE9702762L (sv) 1999-01-22

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Legal Events

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B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

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B09B Patent application refused [chapter 9.2 patent gazette]

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