BR9814290A - Acumulador de traços fora de fontes deinformações para reprodução de instrução apósespeculação defeituosa - Google Patents
Acumulador de traços fora de fontes deinformações para reprodução de instrução apósespeculação defeituosaInfo
- Publication number
- BR9814290A BR9814290A BR9814290-9A BR9814290A BR9814290A BR 9814290 A BR9814290 A BR 9814290A BR 9814290 A BR9814290 A BR 9814290A BR 9814290 A BR9814290 A BR 9814290A
- Authority
- BR
- Brazil
- Prior art keywords
- instructions
- trace
- speculation
- accumulator
- defective
- Prior art date
Links
- 230000002950 deficient Effects 0.000 title abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/1407—Checkpointing the instruction stream
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Advance Control (AREA)
- Debugging And Monitoring (AREA)
Abstract
Patente de Invenção: "ACUMULADOR DE TRAçOS FORA DEFONTES DE INFORMAçõES PARA REPRODUçãO DEINSTRUçãO APóS ESPECULAçãO DEFEITUOSA". Em umamodalidade da invenção, um processador (10) inclui uma fonte deinformações de execução para executar as instruções, em quepelos menos algumas das instruções são executadasespeculativamente. O processador também inclui um acumuladorde traços (114) fora da fonte de informações de execução paraconter as instruções, e em que as instruções que estão associadascom os erros de especulação são reproduzidas na fonte deinformações de execução para executar as instruções, em quepelo menos algumas das instruções são executadasespeculativamente. O processador também inclui um acumuladorde traços fora da fonte de informações de execução para conteras instruções e os resultados da execução das instruções, em quepelo menos algumas das instruções estão sujeitas a umafastamento inicial seguindo a execução na fonte de informações,mas permanecem no acumulador de traços até um afastamentofinal (134).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/991,269 US6240509B1 (en) | 1997-12-16 | 1997-12-16 | Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation |
PCT/US1998/026408 WO1999031589A1 (en) | 1997-12-16 | 1998-12-11 | Out-of-pipeline trace buffer for instruction replay following misspeculation |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9814290A true BR9814290A (pt) | 2001-10-30 |
Family
ID=25537042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9814290-9A BR9814290A (pt) | 1997-12-16 | 1998-12-11 | Acumulador de traços fora de fontes deinformações para reprodução de instrução apósespeculação defeituosa |
Country Status (11)
Country | Link |
---|---|
US (1) | US6240509B1 (pt) |
EP (1) | EP1040421B1 (pt) |
JP (1) | JP3971893B2 (pt) |
KR (1) | KR100382126B1 (pt) |
CN (1) | CN100342349C (pt) |
AU (1) | AU1911099A (pt) |
BR (1) | BR9814290A (pt) |
DE (1) | DE69829778T2 (pt) |
HK (1) | HK1029194A1 (pt) |
TW (1) | TW388811B (pt) |
WO (1) | WO1999031589A1 (pt) |
Families Citing this family (47)
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US6212626B1 (en) * | 1996-11-13 | 2001-04-03 | Intel Corporation | Computer processor having a checker |
US6463522B1 (en) * | 1997-12-16 | 2002-10-08 | Intel Corporation | Memory system for ordering load and store instructions in a processor that performs multithread execution |
US6772324B2 (en) | 1997-12-17 | 2004-08-03 | Intel Corporation | Processor having multiple program counters and trace buffers outside an execution pipeline |
US6412067B1 (en) | 1998-08-11 | 2002-06-25 | Intel Corporation | Backing out of a processor architectural state |
BR9915363B1 (pt) * | 1998-11-16 | 2012-12-25 | sistema de processamento hierÁrquico distribuÍdo com base em eventos, mÉtodo de processamento num sistema de processamento hierÁrquico distribuÍdo com base em eventos, e, sistema de comunicaÇço. | |
SE9901146D0 (sv) * | 1998-11-16 | 1999-03-29 | Ericsson Telefon Ab L M | A processing system and method |
SE9902373D0 (sv) * | 1998-11-16 | 1999-06-22 | Ericsson Telefon Ab L M | A processing system and method |
SE9803901D0 (sv) * | 1998-11-16 | 1998-11-16 | Ericsson Telefon Ab L M | a device for a service network |
SE9901145D0 (sv) | 1998-11-16 | 1999-03-29 | Ericsson Telefon Ab L M | A processing system and method |
US6571359B1 (en) * | 1999-12-13 | 2003-05-27 | Intel Corporation | Systems and methods for testing processors |
US6658554B1 (en) * | 1999-03-09 | 2003-12-02 | Wisconsin Alumni Res Found | Electronic processor providing direct data transfer between linked data consuming instructions |
EP1050807A1 (en) * | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Memory access in a computer memory |
US6463526B1 (en) * | 1999-06-07 | 2002-10-08 | Sun Microsystems, Inc. | Supporting multi-dimensional space-time computing through object versioning |
US7100027B1 (en) * | 1999-12-13 | 2006-08-29 | Intel Corporation | System and method for reproducing system executions using a replay handler |
US6892380B2 (en) * | 1999-12-30 | 2005-05-10 | Texas Instruments Incorporated | Method for software pipelining of irregular conditional control loops |
JP2001209535A (ja) * | 2000-01-27 | 2001-08-03 | Toshiba Corp | プロセッサの命令スケジューリング装置 |
US6609247B1 (en) * | 2000-02-18 | 2003-08-19 | Hewlett-Packard Development Company | Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field |
US6931641B1 (en) | 2000-04-04 | 2005-08-16 | International Business Machines Corporation | Controller for multiple instruction thread processors |
US6880069B1 (en) * | 2000-06-30 | 2005-04-12 | Intel Corporation | Replay instruction morphing |
US6877086B1 (en) * | 2000-11-02 | 2005-04-05 | Intel Corporation | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter |
US6981129B1 (en) * | 2000-11-02 | 2005-12-27 | Intel Corporation | Breaking replay dependency loops in a processor using a rescheduled replay queue |
US7207035B2 (en) * | 2001-08-23 | 2007-04-17 | International Business Machines Corporation | Apparatus and method for converting an instruction and data trace to an executable program |
US7047395B2 (en) * | 2001-11-13 | 2006-05-16 | Intel Corporation | Reordering serial data in a system with parallel processing flows |
US6950924B2 (en) * | 2002-01-02 | 2005-09-27 | Intel Corporation | Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state |
AU2003231945A1 (en) * | 2002-05-31 | 2003-12-19 | Guang R. Gao | Method and apparatus for real-time multithreading |
US7941651B1 (en) | 2002-06-27 | 2011-05-10 | Intel Corporation | Method and apparatus for combining micro-operations to process immediate data |
US7010665B1 (en) | 2002-06-27 | 2006-03-07 | Intel Corporation | Method and apparatus for decompressing relative addresses |
US7111148B1 (en) | 2002-06-27 | 2006-09-19 | Intel Corporation | Method and apparatus for compressing relative addresses |
US7103751B1 (en) | 2002-06-27 | 2006-09-05 | Intel Corporation | Method and apparatus for representation of an address in canonical form |
US7194603B2 (en) * | 2003-04-23 | 2007-03-20 | International Business Machines Corporation | SMT flush arbitration |
US20040225870A1 (en) * | 2003-05-07 | 2004-11-11 | Srinivasan Srikanth T. | Method and apparatus for reducing wrong path execution in a speculative multi-threaded processor |
US20040255104A1 (en) * | 2003-06-12 | 2004-12-16 | Intel Corporation | Method and apparatus for recycling candidate branch outcomes after a wrong-path execution in a superscalar processor |
JP2008523456A (ja) * | 2004-05-12 | 2008-07-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | トレースコプロセッサを備えたデータ処理システム |
US7496735B2 (en) * | 2004-11-22 | 2009-02-24 | Strandera Corporation | Method and apparatus for incremental commitment to architectural state in a microprocessor |
US7508396B2 (en) | 2005-09-28 | 2009-03-24 | Silicon Integrated Systems Corp. | Register-collecting mechanism, method for performing the same and pixel processing system employing the same |
US8219885B2 (en) * | 2006-05-12 | 2012-07-10 | Arm Limited | Error detecting and correcting mechanism for a register file |
US20100306509A1 (en) * | 2009-05-29 | 2010-12-02 | Via Technologies, Inc. | Out-of-order execution microprocessor with reduced store collision load replay reduction |
CN102567137B (zh) * | 2010-12-27 | 2013-09-25 | 北京国睿中数科技股份有限公司 | 在分支预测失败时使用rob恢复rat内容的系统和方法 |
US9612934B2 (en) * | 2011-10-28 | 2017-04-04 | Cavium, Inc. | Network processor with distributed trace buffers |
KR101667167B1 (ko) * | 2012-06-15 | 2016-10-17 | 소프트 머신즈, 인크. | Load store 재정렬 및 최적화로부터 생기는 투기적 포워딩 예측 착오/오류로부터의 복원을 구현하는 방법 및 시스템 |
US9830224B2 (en) * | 2013-03-15 | 2017-11-28 | Nvidia Corporation | Selective fault stalling for a GPU memory pipeline in a unified virtual memory system |
US10209992B2 (en) | 2014-04-25 | 2019-02-19 | Avago Technologies International Sales Pte. Limited | System and method for branch prediction using two branch history tables and presetting a global branch history register |
US9710272B2 (en) | 2014-04-25 | 2017-07-18 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Computer processor with generation renaming |
US9996354B2 (en) | 2015-01-09 | 2018-06-12 | International Business Machines Corporation | Instruction stream tracing of multi-threaded processors |
CN104657145B (zh) * | 2015-03-09 | 2017-12-15 | 上海兆芯集成电路有限公司 | 用于微处理器的重发停靠的系统和方法 |
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CN110688160B (zh) * | 2019-09-04 | 2021-11-19 | 苏州浪潮智能科技有限公司 | 一种指令流水线处理方法、系统、设备及计算机存储介质 |
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US5548776A (en) * | 1993-09-30 | 1996-08-20 | Intel Corporation | N-wide bypass for data dependencies within register alias table |
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US5664137A (en) | 1994-01-04 | 1997-09-02 | Intel Corporation | Method and apparatus for executing and dispatching store operations in a computer system |
US5564028A (en) * | 1994-01-11 | 1996-10-08 | Texas Instruments Incorporated | Pipelined data processing including instruction trace |
US5586278A (en) | 1994-03-01 | 1996-12-17 | Intel Corporation | Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor |
JP3547482B2 (ja) * | 1994-04-15 | 2004-07-28 | 株式会社日立製作所 | 情報処理装置 |
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-
1997
- 1997-12-16 US US08/991,269 patent/US6240509B1/en not_active Expired - Lifetime
-
1998
- 1998-12-11 AU AU19110/99A patent/AU1911099A/en not_active Abandoned
- 1998-12-11 DE DE69829778T patent/DE69829778T2/de not_active Expired - Lifetime
- 1998-12-11 KR KR10-2000-7006657A patent/KR100382126B1/ko not_active IP Right Cessation
- 1998-12-11 BR BR9814290-9A patent/BR9814290A/pt not_active Application Discontinuation
- 1998-12-11 JP JP2000539419A patent/JP3971893B2/ja not_active Expired - Fee Related
- 1998-12-11 WO PCT/US1998/026408 patent/WO1999031589A1/en active IP Right Grant
- 1998-12-11 CN CNB988136562A patent/CN100342349C/zh not_active Expired - Fee Related
- 1998-12-11 EP EP98963873A patent/EP1040421B1/en not_active Expired - Lifetime
- 1998-12-16 TW TW087120952A patent/TW388811B/zh not_active IP Right Cessation
-
2000
- 2000-11-30 HK HK00107676A patent/HK1029194A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW388811B (en) | 2000-05-01 |
DE69829778T2 (de) | 2006-01-26 |
AU1911099A (en) | 1999-07-05 |
CN1286771A (zh) | 2001-03-07 |
DE69829778D1 (de) | 2005-05-19 |
US6240509B1 (en) | 2001-05-29 |
KR100382126B1 (ko) | 2003-05-09 |
WO1999031589A1 (en) | 1999-06-24 |
EP1040421B1 (en) | 2005-04-13 |
EP1040421A4 (en) | 2002-07-17 |
JP3971893B2 (ja) | 2007-09-05 |
KR20010024750A (ko) | 2001-03-26 |
CN100342349C (zh) | 2007-10-10 |
EP1040421A1 (en) | 2000-10-04 |
JP2002508567A (ja) | 2002-03-19 |
HK1029194A1 (en) | 2001-03-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B06A | Patent application procedure suspended [chapter 6.1 patent gazette] | ||
B11B | Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements |