BR9915385A - Processador para uma rede de serviço, e, sistema de processamento para uma rede de serviço - Google Patents

Processador para uma rede de serviço, e, sistema de processamento para uma rede de serviço

Info

Publication number
BR9915385A
BR9915385A BR9915385-8A BR9915385A BR9915385A BR 9915385 A BR9915385 A BR 9915385A BR 9915385 A BR9915385 A BR 9915385A BR 9915385 A BR9915385 A BR 9915385A
Authority
BR
Brazil
Prior art keywords
service network
processor
tasks
task
network
Prior art date
Application number
BR9915385-8A
Other languages
English (en)
Inventor
Per Anders Holmberg
Lars-Irjan Kling
Sten Edward Johnson
Terje Egeland
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9915385A publication Critical patent/BR9915385A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

"PROCESSADOR PARA UMA REDE DE SERVIçO, E, SISTEMA DE PROCESSAMENTO PARA UMA REDE DE SERVIçO" A invenção geralmente relaciona-se a um processador desenvolvido para uma rede de serviço que provê vários serviços para uma pluralidade de usuários conectados à rede. O processador (30; 50) inclui uma fila de tarefa (52) com um número de posições de armazenamento para armazenar sinais de tarefa correspondendo a tarefas que formam parte de serviços substancialmente independentes pedidos pelos usuários da rede, e uma pluralidade de pluralidade de unidades de processamento paralelas (54) que independentemente processam sinais de tarefa de posições de armazenamento diferentes da fila de tarefa (52) para executar tarefas correspondentes em paralelo. Como um número de tarefas é executado de modo especulativo, uma unidade (56) para verificar possíveis dependências entre as tarefas executadas é incorporada no processador. Se uma dependência é detectada para um tarefa especulativo, aquela tarefa é emparelhada. Para assegurar serviço pronto e correto para os usuários da rede de serviço, tarefas emparelhadas são reiniciadas rapidamente e diretamente da fila de tarefa.
BR9915385-8A 1998-11-16 1999-11-12 Processador para uma rede de serviço, e, sistema de processamento para uma rede de serviço BR9915385A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
PCT/SE1999/002060 WO2000029939A1 (en) 1998-11-16 1999-11-12 A job-parallel processor

Publications (1)

Publication Number Publication Date
BR9915385A true BR9915385A (pt) 2001-07-31

Family

ID=20413294

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9915385-8A BR9915385A (pt) 1998-11-16 1999-11-12 Processador para uma rede de serviço, e, sistema de processamento para uma rede de serviço

Country Status (10)

Country Link
EP (1) EP1133725B1 (pt)
JP (1) JP2002530734A (pt)
KR (1) KR20010080469A (pt)
CN (1) CN100492282C (pt)
AU (1) AU1436900A (pt)
BR (1) BR9915385A (pt)
CA (1) CA2350921A1 (pt)
DE (1) DE69943166D1 (pt)
SE (1) SE9803901D0 (pt)
WO (1) WO2000029939A1 (pt)

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WO2003054693A1 (en) * 2001-12-12 2003-07-03 Telefonaktiebolaget L M Ericsson (Publ) Collision handling apparatus and method
JP2003263331A (ja) * 2002-03-07 2003-09-19 Toshiba Corp マルチプロセッサシステム
GB0226249D0 (en) * 2002-11-11 2002-12-18 Clearspeed Technology Ltd Traffic handling system
CN100345132C (zh) * 2003-07-28 2007-10-24 华为技术有限公司 一种并行处理的方法及系统
JP4784827B2 (ja) * 2006-06-06 2011-10-05 学校法人早稲田大学 ヘテロジニアスマルチプロセッサ向けグローバルコンパイラ
KR100856468B1 (ko) 2007-01-08 2008-09-04 재단법인서울대학교산학협력재단 임베디드 소프트웨어의 객체지향 태스크 모델을멀티프로세서 시스템 온 칩 하드웨어 아키텍처로 자동할당하기 위한 방법
CN101656658B (zh) * 2008-08-21 2013-03-20 中兴通讯股份有限公司 一种提高队列管理中出队效率的方法和装置
CN101551758B (zh) * 2009-05-13 2013-06-05 中兴通讯股份有限公司 一种实现设备管理任务并行工作的系统和方法
US9846628B2 (en) 2010-06-15 2017-12-19 Microsoft Technology Licensing, Llc Indicating parallel operations with user-visible events
KR20120017294A (ko) 2010-08-18 2012-02-28 삼성전자주식회사 어플리케이션을 효율적으로 처리하는 스케쥴링 시스템 및 스케쥴링 방법
US8423516B2 (en) * 2010-09-15 2013-04-16 International Business Machines Corporation Speculative execution in a real-time data environment
CN102455932B (zh) * 2010-10-22 2014-06-25 金蝶软件（中国）有限公司 一种任务实例串行执行方法、装置及系统
CN103176862B (zh) * 2011-12-20 2017-03-01 伊姆西公司 用于管理数据备份任务的设备和方法
US9436917B2 (en) * 2013-02-05 2016-09-06 Cisco Technology, Inc. Accelerating learning by sharing information between multiple learning machines
CN104750547B (zh) * 2013-12-31 2018-05-18 华为技术有限公司 虚拟机的输入输出io请求处理方法及装置
FR3038084B1 (fr) * 2015-06-29 2017-12-29 Centre National De La Recherche Scient (C N R S) Microprocesseur parallele stochastique
TWI597666B (zh) * 2015-12-28 2017-09-01 緯創資通股份有限公司 共享裝置的使用方法及資源共享系統
CN107391262B (zh) * 2017-07-31 2020-05-15 李黎黎 一种作业调度方法及装置
CN108491380B (zh) * 2018-03-12 2021-11-23 思必驰科技股份有限公司 用于口语理解的对抗多任务训练方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
DK0661625T3 (da) * 1994-01-03 2000-04-03 Intel Corp Fremgangsmåde og apparatur til implementering af et firetrins system til bestemmelse af programforgreninger (Four Stage Bra
WO1997022927A1 (en) * 1995-12-19 1997-06-26 Telefonaktiebolaget Lm Ericsson (Publ) Job scheduling for instruction processor
US5848257A (en) * 1996-09-20 1998-12-08 Bay Networks, Inc. Method and apparatus for multitasking in a computer system
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
JP2002530734A (ja) 2002-09-17
AU1436900A (en) 2000-06-05
SE9803901D0 (sv) 1998-11-16
CA2350921A1 (en) 2000-05-25
CN1326567A (zh) 2001-12-12
KR20010080469A (ko) 2001-08-22
WO2000029939A1 (en) 2000-05-25
DE69943166D1 (de) 2011-03-10
CN100492282C (zh) 2009-05-27
EP1133725B1 (en) 2011-01-26
EP1133725A1 (en) 2001-09-19

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 10A E 11A ANUIDADE(S).

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2069 DE 31/08/2010.