DE3713992C2 - - Google Patents
Info
- Publication number
- DE3713992C2 DE3713992C2 DE19873713992 DE3713992A DE3713992C2 DE 3713992 C2 DE3713992 C2 DE 3713992C2 DE 19873713992 DE19873713992 DE 19873713992 DE 3713992 A DE3713992 A DE 3713992A DE 3713992 C2 DE3713992 C2 DE 3713992C2
- Authority
- DE
- Germany
- Prior art keywords
- layer
- substance
- nucleation density
- wiring
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02425—Conductive materials, e.g. metallic silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61096866A JPH0828357B2 (ja) | 1986-04-28 | 1986-04-28 | 多層構造の形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3713992A1 DE3713992A1 (de) | 1987-10-29 |
DE3713992C2 true DE3713992C2 (fr) | 1990-10-18 |
Family
ID=14176361
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19873713992 Granted DE3713992A1 (de) | 1986-04-28 | 1987-04-27 | Verfahren zur bildung einer mehrschichtenstruktur |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH0828357B2 (fr) |
DE (1) | DE3713992A1 (fr) |
FR (1) | FR2603738B1 (fr) |
GB (1) | GB2189935B (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0307109A1 (fr) * | 1987-08-24 | 1989-03-15 | Canon Kabushiki Kaisha | Méthode pour former un cristal semi-conducteur et cristal semi-conducteur produit par cette méthode |
GB2216336A (en) * | 1988-03-30 | 1989-10-04 | Philips Nv | Forming insulating layers on substrates |
US5593919A (en) * | 1995-09-05 | 1997-01-14 | Motorola Inc. | Process for forming a semiconductor device including conductive members |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1229093B (de) * | 1963-01-23 | 1966-11-24 | Basf Ag | Verfahren zur Herstellung von Hexahydropyrimidinderivaten |
US3403439A (en) * | 1966-04-29 | 1968-10-01 | Texas Instruments Inc | Electrical isolation of circuit components of monolithic integrated circuits |
CH490515A (de) * | 1967-11-22 | 1970-05-15 | Battelle Development Corp | Verfahren zur Erzeugung von kristallinen Abscheidungen in Form eines Musters auf einer elektrisch isolierenden amorphen, poly- oder einkristallinen Unterlage |
JPS4948286A (fr) * | 1972-09-08 | 1974-05-10 | ||
JPS58200557A (ja) * | 1982-05-18 | 1983-11-22 | Nec Corp | 多層配線の形成方法 |
JPS628543A (ja) * | 1985-07-05 | 1987-01-16 | Fujitsu Ltd | 燐珪酸ガラスの選択成長方法 |
GB2183090B (en) * | 1985-10-07 | 1989-09-13 | Canon Kk | Method for selective formation of deposited film |
-
1986
- 1986-04-28 JP JP61096866A patent/JPH0828357B2/ja not_active Expired - Fee Related
-
1987
- 1987-04-23 GB GB8709569A patent/GB2189935B/en not_active Expired - Lifetime
- 1987-04-27 FR FR8705920A patent/FR2603738B1/fr not_active Expired - Lifetime
- 1987-04-27 DE DE19873713992 patent/DE3713992A1/de active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62254447A (ja) | 1987-11-06 |
DE3713992A1 (de) | 1987-10-29 |
FR2603738A1 (fr) | 1988-03-11 |
GB2189935A (en) | 1987-11-04 |
GB8709569D0 (en) | 1987-05-28 |
GB2189935B (en) | 1990-03-14 |
JPH0828357B2 (ja) | 1996-03-21 |
FR2603738B1 (fr) | 1990-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE2951734C2 (fr) | ||
DE69930839T2 (de) | Herstellungsmethode für eine elekttronische anordnung mit organischen schichten | |
DE4237587C2 (de) | Chemisches Dampfabscheidungsverfahren zur Schaffung einer vorherrschend TiSi¶x¶ enthaltenden, elektrisch leitfähigen Schicht | |
EP0491976B1 (fr) | Méthode de fabrication d'une couche lisse de silicium polycristallin dopé à l'arsenic pour circuits intégrés LSI | |
DE4310955C2 (de) | Verfahren zum Bearbeiten eines Halbleiterwafers | |
DE1903961A1 (de) | Integrierte Halbleiteranordnung | |
WO2001061753A1 (fr) | Composant electronique dote d'une connexion electro-conductrice en nanotubes de carbone et procede de fabrication dudit composant | |
DE69115082T2 (de) | Halbleitervorrichtung mit vielschichtiger Verdrahtungsstruktur und Verfahren zu ihrer Herstellung. | |
DE2445879C2 (de) | Verfahren zum Herstellen eines Halbleiterbauelementes | |
DE69214339T2 (de) | Struktur und Verfahren für die Bildung selbstjustierender Kontakte | |
DE2033532C3 (de) | Halbleiteranordnung mit einer Passivierungsschicht aus Siliziumdioxid | |
DE2430692A1 (de) | Verfahren zum herstellen von verbindungsloechern in isolierschichten | |
DE69114346T2 (de) | Verfahren zum Herstellen von mehrlagigen koplanaren Leitungs-/Isolator-Schichten unter Verwendung von lichtempfindlichem Polyimid. | |
EP0005185A1 (fr) | Procédé pour la formation simultanée de diodes à barrage Schottky et de contacts ohmiques sur des régions semi-conductrices dopées | |
DE10244570A1 (de) | Liner-Schicht mit geringer Stufenüberdeckung zur Verbesserung des Kontaktwiderstands bei W-Kontakten | |
DE19626039A1 (de) | Verfahren zum Herstellen einer Metalleitung | |
DE19608208A1 (de) | Verfahren zur Herstellung von Metallzwischenverbindungen in Halbleitereinrichtungen | |
DE3109074C2 (fr) | ||
DE3636547C2 (fr) | ||
DE3634140C2 (fr) | ||
DE4218495A1 (de) | Halbleiter-vorrichtung und verfahren zur herstellung dieser halbleiter-vorrichtung | |
DE19843624C1 (de) | Integrierte Schaltungsanordnung und Verfahren zu deren Herstellung | |
DE3713992C2 (fr) | ||
DE3888511T2 (de) | Verfahren zum Herstellen von elektrischen Kontakten in integrierten Schaltungen. | |
DE4240565A1 (de) | Halbleitereinrichtung und Verfahren zur Herstellung der Halbleitereinrichtung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: TIEDTKE, H., DIPL.-ING. BUEHLING, G., DIPL.-CHEM. KINNE, R., DIPL.-ING. GRUPE, P., DIPL.-ING. PELLMANN, H., DIPL.-ING. GRAMS, K., DIPL.-ING., PAT.-ANWAELTE, 8000 MUENCHEN |
|
8339 | Ceased/non-payment of the annual fee |