DE3685804T2 - Ttl/cmos-kompatible eingangspufferschaltung. - Google Patents

Ttl/cmos-kompatible eingangspufferschaltung.

Info

Publication number
DE3685804T2
DE3685804T2 DE8686201604T DE3685804T DE3685804T2 DE 3685804 T2 DE3685804 T2 DE 3685804T2 DE 8686201604 T DE8686201604 T DE 8686201604T DE 3685804 T DE3685804 T DE 3685804T DE 3685804 T2 DE3685804 T2 DE 3685804T2
Authority
DE
Germany
Prior art keywords
ttl
input buffer
cmos compatible
buffer switching
compatible input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686201604T
Other languages
English (en)
Other versions
DE3685804D1 (de
Inventor
Hung-Cheng Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE3685804D1 publication Critical patent/DE3685804D1/de
Publication of DE3685804T2 publication Critical patent/DE3685804T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE8686201604T 1985-09-19 1986-09-18 Ttl/cmos-kompatible eingangspufferschaltung. Expired - Lifetime DE3685804T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/778,344 US4820937A (en) 1985-09-19 1985-09-19 TTL/CMOS compatible input buffer

Publications (2)

Publication Number Publication Date
DE3685804D1 DE3685804D1 (de) 1992-07-30
DE3685804T2 true DE3685804T2 (de) 1992-12-17

Family

ID=25113023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686201604T Expired - Lifetime DE3685804T2 (de) 1985-09-19 1986-09-18 Ttl/cmos-kompatible eingangspufferschaltung.

Country Status (5)

Country Link
US (1) US4820937A (de)
EP (1) EP0223267B1 (de)
JP (1) JPS62142416A (de)
CA (1) CA1267196A (de)
DE (1) DE3685804T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783607A (en) * 1986-11-05 1988-11-08 Xilinx, Inc. TTL/CMOS compatible input buffer with Schmitt trigger
US4841175A (en) * 1987-01-23 1989-06-20 Siemens Aktiengesellschaft ECL-compatible input/output circuits in CMOS technology
JPS63305616A (ja) * 1987-06-08 1988-12-13 Sony Corp 信号レベル変換回路
US4763021A (en) * 1987-07-06 1988-08-09 Unisys Corporation CMOS input buffer receiver circuit with ultra stable switchpoint
US4857770A (en) * 1988-02-29 1989-08-15 Advanced Micro Devices, Inc. Output buffer arrangement for reducing chip noise without speed penalty
US4833350A (en) * 1988-04-29 1989-05-23 Tektronix, Inc. Bipolar-CMOS digital interface circuit
US5280200A (en) * 1989-04-10 1994-01-18 Tarng Min M Pipelined buffer for analog signal and power supply
JPH0334719A (ja) * 1989-06-30 1991-02-14 Toshiba Micro Electron Kk 半導体集積回路
US4999529A (en) * 1989-06-30 1991-03-12 At&T Bell Laboratories Programmable logic level input buffer
US5322812A (en) * 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5311084A (en) * 1992-06-23 1994-05-10 At&T Bell Laboratories Integrated circuit buffer with controlled rise/fall time
US5361229A (en) * 1993-04-08 1994-11-01 Xilinx, Inc. Precharging bitlines for robust reading of latch data
JPH0757465A (ja) * 1993-08-06 1995-03-03 Mitsubishi Electric Corp 半導体回路装置
US5410189A (en) * 1993-09-27 1995-04-25 Xilinx, Inc. Input buffer having an accelerated signal transition
KR100392556B1 (ko) * 1994-01-31 2003-11-12 주식회사 하이닉스반도체 시모스회로용입력버퍼
US5786720A (en) * 1994-09-22 1998-07-28 Lsi Logic Corporation 5 volt CMOS driver circuit for driving 3.3 volt line
US5970255A (en) 1995-10-16 1999-10-19 Altera Corporation System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
US5691654A (en) * 1995-12-14 1997-11-25 Cypress Semiconductor Corp. Voltage level translator circuit
US5666069A (en) * 1995-12-22 1997-09-09 Cypress Semiconductor Corp. Data output stage incorporating an inverting operational amplifier
US6038260A (en) * 1996-01-05 2000-03-14 International Business Machines Corporation Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
US5751166A (en) * 1996-06-04 1998-05-12 Motorola, Inc. Input buffer circuit and method
DE19739806A1 (de) * 1997-09-10 1999-03-11 Siemens Ag Eingangsschaltung mit steuerbarer Schaltschwelle
US6836151B1 (en) 1999-03-24 2004-12-28 Altera Corporation I/O cell configuration for multiple I/O standards
US6271679B1 (en) 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards
US6911860B1 (en) 2001-11-09 2005-06-28 Altera Corporation On/off reference voltage switch for multiple I/O standards
US7301370B1 (en) * 2003-05-22 2007-11-27 Cypress Semiconductor Corporation High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
US7109770B1 (en) * 2004-03-08 2006-09-19 Altera Corporation Programmable amplifiers with positive and negative hysteresis
CN100352164C (zh) * 2004-11-16 2007-11-28 矽成积体电路股份有限公司 用于降低功率消耗的输入缓冲器电路
CN100353667C (zh) * 2004-11-16 2007-12-05 矽成积体电路股份有限公司 用于稳定逻辑转换点的输入缓冲器电路

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE227843C (de) *
US4032795A (en) * 1976-04-14 1977-06-28 Solitron Devices, Inc. Input buffer
DE2708021C3 (de) * 1977-02-24 1984-04-19 Eurosil GmbH, 8000 München Schaltungsanordnung in integrierter CMOS-Technik zur Regelung der Speisespannung für eine Last
US4258272A (en) * 1979-03-19 1981-03-24 National Semiconductor Corporation TTL to CMOS input buffer circuit
US4438352A (en) * 1980-06-02 1984-03-20 Xerox Corporation TTL Compatible CMOS input buffer
US4430582A (en) * 1981-11-16 1984-02-07 National Semiconductor Corporation Fast CMOS buffer for TTL input levels
US4471242A (en) * 1981-12-21 1984-09-11 Motorola, Inc. TTL to CMOS Input buffer
US4475050A (en) * 1981-12-21 1984-10-02 Motorola, Inc. TTL To CMOS input buffer
US4490633A (en) * 1981-12-28 1984-12-25 Motorola, Inc. TTL to CMOS input buffer
US4469959A (en) * 1982-03-15 1984-09-04 Motorola, Inc. Input buffer
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
DE3323446A1 (de) * 1983-06-29 1985-01-10 Siemens AG, 1000 Berlin und 8000 München Eingangssignalpegelwandler fuer eine mos-digitalschaltung
JPS6070822A (ja) * 1983-09-28 1985-04-22 Hitachi Ltd 半導体集積回路
US4563595A (en) * 1983-10-27 1986-01-07 National Semiconductor Corporation CMOS Schmitt trigger circuit for TTL logic levels
US4504747A (en) * 1983-11-10 1985-03-12 Motorola, Inc. Input buffer circuit for receiving multiple level input voltages
US4612461A (en) * 1984-02-09 1986-09-16 Motorola, Inc. High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
US4584492A (en) * 1984-08-06 1986-04-22 Intel Corporation Temperature and process stable MOS input buffer
DD227843A1 (de) * 1984-10-10 1985-09-25 Mikroelektronik Zt Forsch Tech Cmos-eingangspegelwandler
JPS60143012A (ja) * 1984-10-24 1985-07-29 Hitachi Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
EP0223267A1 (de) 1987-05-27
US4820937A (en) 1989-04-11
EP0223267B1 (de) 1992-06-24
CA1267196A (en) 1990-03-27
DE3685804D1 (de) 1992-07-30
JPS62142416A (ja) 1987-06-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee