DE3781919D1 - Eingangsschaltung. - Google Patents

Eingangsschaltung.

Info

Publication number
DE3781919D1
DE3781919D1 DE8787104523T DE3781919T DE3781919D1 DE 3781919 D1 DE3781919 D1 DE 3781919D1 DE 8787104523 T DE8787104523 T DE 8787104523T DE 3781919 T DE3781919 T DE 3781919T DE 3781919 D1 DE3781919 D1 DE 3781919D1
Authority
DE
Germany
Prior art keywords
input switching
switching
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787104523T
Other languages
English (en)
Other versions
DE3781919T2 (de
Inventor
Kazunori C O Patent Di Tsugaru
Yasuhiro C O Patent D Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3781919D1 publication Critical patent/DE3781919D1/de
Publication of DE3781919T2 publication Critical patent/DE3781919T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE8787104523T 1986-03-31 1987-03-26 Eingangsschaltung. Expired - Fee Related DE3781919T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61072843A JPS62230222A (ja) 1986-03-31 1986-03-31 入力回路

Publications (2)

Publication Number Publication Date
DE3781919D1 true DE3781919D1 (de) 1992-11-05
DE3781919T2 DE3781919T2 (de) 1993-02-18

Family

ID=13501075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787104523T Expired - Fee Related DE3781919T2 (de) 1986-03-31 1987-03-26 Eingangsschaltung.

Country Status (5)

Country Link
US (1) US4798981A (de)
EP (1) EP0239939B1 (de)
JP (1) JPS62230222A (de)
KR (1) KR900004591B1 (de)
DE (1) DE3781919T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2585599B2 (ja) * 1987-06-05 1997-02-26 株式会社日立製作所 出力インタ−フエ−ス回路
US4857766A (en) * 1987-10-30 1989-08-15 International Business Machine Corporation BiMos input circuit
US5144163A (en) * 1988-03-14 1992-09-01 Matsushita Electric Industrial Co., Ltd. Dynamic BiCMOS logic gates
JPH06103839B2 (ja) * 1988-12-28 1994-12-14 株式会社東芝 半導体論理回路
US5001362A (en) * 1989-02-14 1991-03-19 Texas Instruments Incorporated BiCMOS reference network
US4914321A (en) * 1989-04-10 1990-04-03 Motorola, Inc. BIMOS level convertor
JP2549729B2 (ja) * 1989-04-26 1996-10-30 株式会社東芝 半導体集積回路
JP2540971B2 (ja) * 1990-03-13 1996-10-09 日本電気株式会社 レベル変換回路
JP2800522B2 (ja) * 1992-02-03 1998-09-21 日本電気株式会社 電流切換回路
US5264745A (en) * 1992-08-28 1993-11-23 Advanced Micro Devices, Inc. Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator
JP3257504B2 (ja) * 1998-03-30 2002-02-18 株式会社日立製作所 半導体記憶装置
US6362652B1 (en) 1999-12-20 2002-03-26 Fujitsu Microelectronics, Inc. High voltage buffer for submicron CMOS

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56106427A (en) * 1980-01-25 1981-08-24 Mitsubishi Electric Corp Transister logical circuit
JPS585029A (ja) * 1981-06-30 1983-01-12 Fujitsu Ltd レベル変換回路
DE3217512A1 (de) * 1982-05-10 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur pegelumsetzung
US4453095A (en) * 1982-07-16 1984-06-05 Motorola Inc. ECL MOS Buffer circuits
JPS59215122A (ja) * 1983-05-23 1984-12-05 Fujitsu Ltd トランジスタ回路
JPH0720059B2 (ja) * 1984-05-23 1995-03-06 株式会社日立製作所 トランジスタ回路
JPS6157118A (ja) * 1984-08-29 1986-03-24 Toshiba Corp レベル変換回路
US4677320A (en) * 1985-05-02 1987-06-30 Fairchild Semiconductor Corporation Emitter coupled logic to transistor transistor logic translator
JPS6269719A (ja) * 1985-09-24 1987-03-31 Toshiba Corp レベル変換論理回路

Also Published As

Publication number Publication date
EP0239939A2 (de) 1987-10-07
KR900004591B1 (ko) 1990-06-30
KR870009478A (ko) 1987-10-27
DE3781919T2 (de) 1993-02-18
EP0239939B1 (de) 1992-09-30
EP0239939A3 (en) 1988-12-14
US4798981A (en) 1989-01-17
JPS62230222A (ja) 1987-10-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee